Jaerok Kim

Orcid: 0000-0002-4086-5215

According to our database1, Jaerok Kim authored at least 5 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 6T-SRAM-Based Physically-Unclonable-Function With Low BER Through Automated Maximum Mismatch Detection.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2024

2022
Variation-Tolerant and Low R-Ratio Compute-in-Memory ReRAM Macro With Capacitive Ternary MAC Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Logic-embedded Physically Unclonable Functions for Synthesizable and Periphery-free Implementation for Low Area and Design Cost IoT Security.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021
A Charge-Domain Scalable-Weight In-Memory Computing Macro With Dual-SRAM Architecture for Precision-Scalable DNN Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021


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