Johnny Rhe
Orcid: 0000-0003-2603-974X
According to our database1,
Johnny Rhe
authored at least 8 papers
between 2021 and 2023.
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Bibliography
2023
PAIRS: Pruning-AIded Row-Skipping for SDK-Based Convolutional Weight Mapping in Processing-In-Memory Architectures.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
DCR: Decomposition-Aware Column Re-Mapping for Stuck-At-Fault Tolerance in ReRAM Arrays.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
2022
VWC-SDK: Convolutional Weight Mapping Using Shifted and Duplicated Kernel With Variable Windows and Channels.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
VW-SDK: Efficient Convolutional Weight Mapping Using Variable Windows for Processing-In-Memory Architectures.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
A Charge-Domain Scalable-Weight In-Memory Computing Macro With Dual-SRAM Architecture for Precision-Scalable DNN Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021