Jaeyong Lee

Orcid: 0000-0002-0073-2733

Affiliations:

Soongsil University, Department of Electronic Engineering, Seoul, Korea

According to our database¹, Jaeyong Lee authored at least 5 papers between 2023 and 2025.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of five.

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Bibliography

2025

Design of Compact Size CMOS VCO Using Dual-Primary Transformer With Dual-Core for Wide Tuning-Range.

[BibT_eX]

[DOI]

Joonseok Park

Jaeyong Lee

Changkun Park

IEEE Trans. Circuits Syst. II Express Briefs, September, 2025

2.4-GHz CMOS Power Amplifier With Common-Mode Self-Rejection Technique to Suppress Even Harmonics.

[BibT_eX]

[DOI]

IEEE Access, 2025

2024

Asymmetric SOI CMOS Switch With Series and Parallel Resonators to Enhance Isolation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Ka-Band CMOS Power Amplifier Using Stacked Structure With Cascode-Like Operation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

2023

A Ka-Band 3-Bit GaN Digital Step Attenuator Using Phase Compensation Method.

[BibT_eX]

[DOI]

IEEE Access, 2023

Jaeyong Lee

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Bibliography

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