Joonseok Park

Orcid: 0009-0005-4132-3353

According to our database1, Joonseok Park authored at least 31 papers between 1999 and 2026.

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Bibliography

2026
Hybrid-Oxide Two-Stacked-FET CMOS Power Amplifier With Optimized Gate Impedance for X-Band Applications.
IEEE Access, 2026

2025
Private cloud bespoke orchestrator: techniques for constructing and operating bespoke-private cloud virtual machine environments for cloud users.
J. Cloud Comput., December, 2025

Design of Compact Size CMOS VCO Using Dual-Primary Transformer With Dual-Core for Wide Tuning-Range.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2025

Blockchain transaction refinery: a traceability refinement mechanism to improve the analysis of permissioned blockchain transactions.
J. King Saud Univ. Comput. Inf. Sci., 2025

2023
Enhancing Security of Web-Based IoT Services via XSS Vulnerability Detection.
Sensors, December, 2023

Smart Contract Broker: Improving Smart Contract Reusability in a Blockchain Environment.
Sensors, July, 2023

2019
Efficient video quality assessment for on-demand video transcoding using intensity variation analysis.
J. Supercomput., 2019

2015
Program-Invariant Checking for Soft-Error Detection using Reconfigurable Hardware.
ACM Trans. Reconfigurable Technol. Syst., 2015

2014
Event classification for vehicle navigation system by regional optical flow analysis.
Mach. Vis. Appl., 2014

Evaluating High-Level Program Invariants Using Reconfigurable Hardware.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2011
Data Reorganization and Prefetching of Pointer-Based Data Structures.
IEEE Des. Test Comput., 2011

2009
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Delay Analysis of Car-to-Car Reliable Data Delivery Strategies Based on Data Mulling with Network Coding.
IEICE Trans. Inf. Syst., 2008

Simultaneous thin-thread processors for low-power embedded systems.
IEICE Electron. Express, 2008

2007
Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2005
Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system.
Microprocess. Microsystems, 2005

2004
Extending the Applicability of Scalar Replacement to Multiple Induction Variables.
Proceedings of the Languages and Compilers for High Performance Computing, 2004

Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract.
Proceedings of the Field Programmable Logic and Application, 2004

2003
Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Using FPGAs for data and reorganization engines: preliminary results for spatial pointer-based data structures.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Performance and Area Modeling of Complete FPGA Designs in the presence of Loop Transformations.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing Engines.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

2002
Data reorganization engines for the next generation of system-on-a-chip FPGAs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

2001
Bridging the Gap between Compilation and Synthesis in the DEFACTO System.
Proceedings of the Languages and Compilers for Parallel Computing, 2001

Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Matching and searching analysis for parallel hardware implementation on FPGAs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

An External Memory Interface for FPGA-Based Computing Engines.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

2000
Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
Mapping Irregular Applications to DIVA, a PIM-based Data-Intensive Architecture.
Proceedings of the ACM/IEEE Conference on Supercomputing, 1999


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