James Vandersand

According to our database, James Vandersand authored at least 4 papers between 2005 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A 0.29pJ/b 5.27Tb/s/mm UCIe Advanced Package Link in 3nm FinFET with 2.5D CoWoS Packaging.

Didem Turker Melek, R. Navinkumar, James Vandersand, Pyare Sarkar, BS Prakash, Adrian Leuciuc, Kevin Geary, Shaojun Ma, Chirag Mukesh Mehta, Shashi Jain, Basant Bothra, Pawan Sabharwal, Ranjan Vaish, Kirti Bhanushali, Yutong Ding, Craig Frost, John Annunziata, Krishanu Sadhu, Dimitris Kyritsis, Jeff Bostak, Ming Li, Steve Williams, Ken Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2023

Short to Medium-Reach Wireline Transceivers Using Single-Ended Signaling, Clock Forwarding, and Spatial Encoding for Die-to-Die Applications.

Scott D. Huss, Chris Moscone, Mark Summers, James Vandersand, Kelvin McCollough, Randall Smith

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2021

A 480Gb/s/mm 1.7pJ/b Short-Reach Wireline Transceiver Using Single-Ended NRZ for Die-to-Die Applications.

Kelvin McCollough, Scott D. Huss, James Vandersand, Randall Smith, Chris Moscone, Qazi Omar Farooq

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2005

SOI four-gate transistors (G⁴-FETs) for high voltage analog applications.

Suheng Chen, James Vandersand, Benjamin J. Blalock, Kerem Akarvardar, Sorin Cristoloveanu, Mohammad M. Mojarradi

Proceedings of the 31st European Solid-State Circuits Conference, 2005