Kerem Akarvardar

Orcid: 0000-0001-5957-826X

According to our database1, Kerem Akarvardar authored at least 15 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm<sup>2</sup> and 3.78Mb/mm<sup>2</sup> Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
Technology Prospects for Data-Intensive Computing.
Proc. IEEE, 2023

A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
A 5-nm 254-TOPS/W 221-TOPS/mm<sup>2</sup> Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS.
IEEE J. Solid State Circuits, 2021

An 89TOPS/W and 16.3TOPS/mm<sup>2</sup> All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
Scanning the Issue.
Proc. IEEE, 2020

A Density Metric for Semiconductor Technology [Point of View].
Proc. IEEE, 2020

2010
Efficient FPGAs using nanoelectromechanical relays.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009
Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2007
High-temperature performance of state-of-the-art triple-gate transistors.
Microelectron. Reliab., 2007

2005
The G<sup>4</sup>-FET: a universal and programmable logic gate.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

SOI four-gate transistors (G<sup>4</sup>-FETs) for high voltage analog applications.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

A novel four-quadrant analog multiplier using SOI four-gate transistors (G<sup>4</sup>-FETs).
Proceedings of the 31st European Solid-State Circuits Conference, 2005


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