Kerem Akarvardar
Orcid: 0000-0001-5957-826X
According to our database1,
Kerem Akarvardar authored at least 23 papers
between 2005 and 2026.
Collaborative distances:
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Bibliography
2026
A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm<sup>2</sup>-17 TFLOPS/mm<sup>2</sup> SRAM-Based INT8, and FP16 Digital-CIM Compiler With Support for Multi-Weight Update/Cycle.
IEEE J. Solid State Circuits, April, 2026
Ultrafast Generative AI by Ultradense 3D Integration: A Case Study on LLM-based Edge Inference.
ACM Trans. Design Autom. Electr. Syst., January, 2026
Exploration of Algorithm-Hardware Co-Design for Floating-Point Digital Compute-in-Memory.
IEEE Comput. Archit. Lett., 2026
2025
Clo-HDnn: A 4.66 TFLOPS/W and 3.78 TOPS/W Continual On-Device Learning Accelerator with Energy-efficient Hyperdimensional Computing via Progressive Search.
CoRR, July, 2025
IEEE Comput. Archit. Lett., 2025
Finding the Pareto Frontier of Low-Precision Data Formats and MAC Architecture for LLM Inference.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025
2024
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024
Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework.
ACM Trans. Design Autom. Electr. Syst., 2024
34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm<sup>2</sup> and 3.78Mb/mm<sup>2</sup> Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024
2023
A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 5-nm 254-TOPS/W 221-TOPS/mm<sup>2</sup> Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS.
IEEE J. Solid State Circuits, 2021
An 89TOPS/W and 16.3TOPS/mm<sup>2</sup> All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
2010
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010
2009
Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
2007
Microelectron. Reliab., 2007
2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
A novel four-quadrant analog multiplier using SOI four-gate transistors (G<sup>4</sup>-FETs).
Proceedings of the 31st European Solid-State Circuits Conference, 2005