Ken Chang

According to our database1, Ken Chang authored at least 100 papers between 2003 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
FDU-Net: Deep Learning-Based Three-Dimensional Diffuse Optical Image Reconstruction.
IEEE Trans. Medical Imaging, 2023

A Deep Learning Based Framework for Joint Image Registration and Segmentation of Brain Metastases on Magnetic Resonance Imaging.
Proceedings of the Machine Learning for Healthcare Conference, 2023

2022
An automated COVID-19 triage pipeline using artificial intelligence based on chest radiographs and clinical data.
npj Digit. Medicine, 2022

How Machine Learning is Powering Neuroimaging to Improve Brain Health.
Neuroinformatics, 2022

Three Applications of Conformal Prediction for Rating Breast Density in Mammography.
CoRR, 2022

Federated Learning Enables Big Data for Rare Cancer Boundary Detection.
CoRR, 2022

Decreasing Annotation Burden of Pairwise Comparisons with Human-in-the-Loop Sorting: Application in Medical Image Artifact Rating.
CoRR, 2022

Is this good enough? On expert perception of brain tumor segmentation quality.
Proceedings of the Medical Imaging 2022: Image Perception, 2022

Do I know this? segmentation uncertainty under domain shift.
Proceedings of the Medical Imaging 2022: Image Processing, 2022

Towards More Efficient Data Valuation in Healthcare Federated Learning Using Ensembling.
Proceedings of the Distributed, Collaborative, and Federated Learning, and Affordable AI and Healthcare for Resource Diverse Global Health, 2022

Fair Conformal Predictors for Applications in Medical Imaging.
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

2021
DeepNeuro: an open-source deep learning toolbox for neuroimaging.
Neuroinformatics, 2021

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET.
IEEE J. Solid State Circuits, 2021

QU-BraTS: MICCAI BraTS 2020 Challenge on Quantifying Uncertainty in Brain Tumor Segmentation - Analysis of Ranking Metrics and Benchmarking Results.
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CoRR, 2021

Deploying clinical machine learning? Consider the following...
CoRR, 2021

Addressing catastrophic forgetting for medical domain expansion.
CoRR, 2021


Opportunities and Challenges for Deep Learning in Brain Lesions.
Proceedings of the Brainlesion: Glioma, Multiple Sclerosis, Stroke and Traumatic Brain Injuries, 2021

2020
Siamese neural networks for continuous disease severity evaluation and change detection in medical imaging.
npj Digit. Medicine, 2020

Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET.
IEEE J. Solid State Circuits, 2020

Corrigendum to: Accounting for data variability in multi-institutional distributed deep learning for medical imaging.
J. Am. Medical Informatics Assoc., 2020

Accounting for data variability in multi-institutional distributed deep learning for medical imaging.
J. Am. Medical Informatics Assoc., 2020

The unreasonable effectiveness of Batch-Norm statistics in addressing catastrophic forgetting across medical institutions.
CoRR, 2020

Towards Trainable Saliency Maps in Medical Imaging.
CoRR, 2020

Assessing the (Un)Trustworthiness of Saliency Maps for Localizing Abnormalities in Medical Imaging.
CoRR, 2020

Assessing the validity of saliency maps for abnormality localization in medical imaging.
CoRR, 2020

An exploration of uncertainty information for segmentation quality assessment.
Proceedings of the Medical Imaging 2020: Image Processing, 2020


Radiomics and Radiogenomics with Deep Learning in Neuro-oncology.
Proceedings of the Machine Learning in Clinical Neuroimaging and Radiogenomics in Neuro-oncology, 2020

6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET.
Proceedings of the European Conference on Optical Communications, 2020

Segmentation, Survival Prediction, and Uncertainty Estimation of Gliomas from Multimodal 3D MRI Using Selective Kernel Networks.
Proceedings of the Brainlesion: Glioma, Multiple Sclerosis, Stroke and Traumatic Brain Injuries, 2020

2019
A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.
IEEE J. Solid State Circuits, 2019

Introduction to the Special Issue on the 2018 Symposium on VLSI Circuits.
IEEE J. Solid State Circuits, 2019

Split Learning for collaborative deep learning in healthcare.
CoRR, 2019

Give me (un)certainty - An exploration of parameters that affect segmentation uncertainty.
CoRR, 2019

ExpertMatcher: Automating ML Model Selection for Clients using Hidden Representations.
CoRR, 2019

ExpertMatcher: Automating ML Model Selection for Users in Resource Constrained Countries.
CoRR, 2019

A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
AnatomiCuts: Hierarchical clustering of tractography streamlines based on anatomical similarity.
NeuroImage, 2018

Introduction to the Special Issue on the 2017 Symposium on VLSI Circuits.
IEEE J. Solid State Circuits, 2018

Distributed deep learning networks among institutions for medical imaging.
J. Am. Medical Informatics Assoc., 2018

Semi-Supervised Deep Learning for Abnormality Classification in Retinal Images.
CoRR, 2018

Deep feature transfer between localization and segmentation tasks.
CoRR, 2018

DeepNeuro: an open-source deep learning toolbox for neuroimaging.
CoRR, 2018

High-resolution medical image synthesis using progressively grown generative adversarial networks.
CoRR, 2018

An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 112-GB/S PAM4 Transmitter in 16NM FinFET.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Sequential neural networks for biologically-informed glioma segmentation.
Proceedings of the Medical Imaging 2018: Image Processing, 2018

A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 56 Gb/s 6 mW 300 um<sup>2</sup> inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET.
IEEE J. Solid State Circuits, 2017

A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET.
IEEE J. Solid State Circuits, 2017

A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET.
IEEE J. Solid State Circuits, 2017

A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS.
IEEE J. Solid State Circuits, 2017

Institutionally Distributed Deep Learning Networks.
CoRR, 2017

Sequential 3D U-Nets for Biologically-Informed Brain Tumor Segmentation.
CoRR, 2017

6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET.
IEEE J. Solid State Circuits, 2016

A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 7-to-18.3GHz compact transformer based VCO in 16nm FinFET.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Hierarchical Clustering of Tractography Streamlines Based on Anatomical Similarity.
Proceedings of the Medical Image Computing and Computer-Assisted Intervention - MICCAI 2016, 2016

3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS.
IEEE J. Solid State Circuits, 2015

3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links: Wireline subcommittee.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
F6: Energy-efficient I/O design for next-generation systems.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs.
IEEE J. Solid State Circuits, 2013

A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver.
IEEE J. Solid State Circuits, 2013

Session 2 overview: Ultra-high-speed transceivers and equalizers.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

F2: VLSI power-management techniques: Principles and applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.
IEEE J. Solid State Circuits, 2012

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.
IEEE J. Solid State Circuits, 2012

A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link.
IEEE J. Solid State Circuits, 2012

A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

10-40 Gb/s I/O design for data communications.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Session 19 overview: 20+ Gb/s wireline transceivers and injection-locked clocking: Wireline subcommittee.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Design of high-speed wireline transceivers for backplane communications in 28nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Ultra-low voltage VLSIs for energy efficient systems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
Low-skew clock distribution using zero-phase-clock-buffer DLLs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface.
IEEE J. Solid State Circuits, 2009

2008
Clocking circuits for a 16Gb/s memory interface.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Session 20 - Advanced wireline techniques.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2006
Replica compensated linear regulators for supply-regulated phase-locked loops.
IEEE J. Solid State Circuits, 2006

2003
A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs.
IEEE J. Solid State Circuits, 2003


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