Jan Pottgiesser

According to our database, Jan Pottgiesser authored at least 5 papers between 2003 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling.

Timothy M. Hollis, Ronny Schneider, Martin Brox, Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon Garrido, David Ovard, Karl Pfefferl, Sven Piatkowski, Gabriele Piscopo, Manfred Plan, Jens Polney, Jan Pottgiesser, Stephan Rau, Filippo Vitale, Marc Walter, Marcos Alvarez Gonzalez, Cristian Chetreanu, Andrea Sorrentino, Jörg Weller, Peter Mayer, Michael Richter, Casto Salobrena Garcia, Andreas Schneider, Shih Nern Wong

IEEE J. Solid State Circuits, 2022

2021

25.3 An 8Gb GDDR6X DRAM Achieving 22Gb/s/pin with Single-Ended PAM4 Signaling.

Timothy M. Hollis, Ronny Schneider, Martin Brox, Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon Garrido, David Ovard, Karl Pfefferl, Sven Piatkowski, Gabriele Piscopo, Manfred Plan, Jens Polney, Jan Pottgiesser, Stephan Rau, Filippo Vitale, Marc Walter, Marcos Alvarez Gonzalez, Martin Broschwitz, Cristian Chetreanu, Andrea Sorrentino, Jörg Weller, Peter Mayer, Michael Richter, Casto Salobrena Garcia, Andreas Schneider, Shih Nern Wong

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2018

An 8-Gb 12-Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications.

Martin Brox, Mani Balakrishnan, Martin Broschwitz, Cristian Chetreanu, Stefan Dietrich, Fabien Funfrock, Marcos Alvarez Gonzalez, Thomas Hein, Eugen Huber, Daniel Lauber, Milena Ivanov, Maksim Kuzmenka, Chris Mohr, Juan Ocon Garrido, Swetha Padaraju, Sven Piatkowski, Jan Pottgiesser, Peter Pfefferl, Manfred Plan, Jens Polney, Stephan Rau, Michael Richter, Ronny Schneider, Ralf Oliver Seitter, Wolfgang Spirkl, Marc Walter, Jörg Weller, Filippo Vitale

IEEE J. Solid State Circuits, 2018

2017

23.1 An 8Gb 12Gb/s/pin GDDR5X DRAM for cost-effective high-performance applications.

Martin Brox, Mani Balakrishnan, Martin Broschwitz, Cristian Chetreanu, Stefan Dietrich, Fabien Funfrock, Marcos Alvarez Gonzalez, Thomas Hein, Eugen Huber, Daniel Lauber, Milena Ivanov, Maksim Kuzmenka, Chris Mohr, Francisco Emiliano Munoz, Juan Ocon Garrido, Swetha Padaraju, Sven Piatkowski, Jan Pottgiesser, Peter Pfefferl, Manfred Plan, Jens Polney, Stefan Rau, Michael Richter, Ronny Schneider, Ralf Oliver Seitter, Wolfgang Spirkl, Marc Walter, Jörg Weller, Filippo Vitale

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2003

MALTY--A memory test structure for analysis in the early phase of the technology development.

Thomas Nirschl, M. Ostermayr, A. Olbrich, D. Vietzke, M. Omer, Carsten Linnenbank, U. Schaper, Y. Pottgiesser, Jan Pottgiesser, M. Johansson

Microelectron. Reliab., 2003