Jörg Weller

According to our database1, Jörg Weller authored at least 8 papers between 1991 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2022
An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling.
IEEE J. Solid State Circuits, 2022

2021

2018
An 8-Gb 12-Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications.
IEEE J. Solid State Circuits, 2018

2017

2010
A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques.
IEEE J. Solid State Circuits, 2010

2009

2006
A 2Gb/s/pin 512Mb Graphics DRAM with NoiseReduction Techniques.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

1991
Organisatorische Anforderungen an ein Netzmanagementsystem zur Verwaltung heterogener Netze.
Proceedings of the Organisation und Betrieb von Informationssystemen, 1991


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