Janardhan H. Satyanarayana

According to our database1, Janardhan H. Satyanarayana authored at least 8 papers between 1996 and 2000.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2000
Power Estimation of Digital Data Paths Using HEAT.
IEEE Des. Test Comput., 2000

1999
Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1997
A New Technique for the High-Level Synthesis of Digit-Serial Digital Filters Based on Genetic Algorithms.
J. Circuits Syst. Comput., 1997

Design and Implementation of Low-Power Digit-Serial Multipliers.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
Design and FPGA Implementation of Digit-Serial Modified Booth Multipliers.
J. Circuits Syst. Comput., 1996

Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

A hierarchical approach to transistor-level power estimation of arithmetic units.
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

HEAT: Hierarchical Energy Analysis Tool.
Proceedings of the 33st Conference on Design Automation, 1996


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