Yun-Nan Chang

According to our database1, Yun-Nan Chang authored at least 31 papers between 1996 and 2023.

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Bibliography

2023
Design of Low-cost IOU Circuit for Post-processing of Object Detection.
Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

2019
Scaling Bit-Flexible Neural Networks.
Proceedings of the 2019 International SoC Design Conference, 2019

Design of A Bit-Serial Artificial Neuron VLSI Architecture with Early Termination.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019

2017
A fast ray tracing scheme for dynamic scenes.
Proceedings of the 4th International Conference on Control, 2017

2016
Design of an area-efficient partial-sum architecture for polar decoders based on new matrix generator.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2015
An Efficient Curve-Scanline Intersection Locator Design for 2D Graphics Rendering.
J. Signal Process. Syst., 2015

An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support.
Proceedings of the VLSI Design, Automation and Test, 2015

2014
Design of a 2D graphics front-end rendering processor.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
Efficient Vector Graphics Rasterization Accelerator Using Optimized Scan-Line Buffer.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Two-level hierarchical fill-buffer for graphics rendering systems.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Architectures for digital filters using stochastic computing.
Proceedings of the IEEE International Conference on Acoustics, 2013

2010
Digit-Serial Pipeline Sorter Architecture.
J. Signal Process. Syst., 2010

A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2009
A Fast Spline Curve Rendering Accelerator Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Lossless Buffer Compression Scheme for 3D Graphic System.
Proceedings of the 2009 International Conference on Computer Graphics & Virtual Reality, 2009

An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
An Efficient Design of H.264 Inter Interpolator with Bandwidth Optimization.
J. Signal Process. Syst., 2008

A low-cost dual-mode deinterleaver design.
IEEE Trans. Consumer Electron., 2008

An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

2005
Design of an efficient memory-based DVB-T channel decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
An Efficient In-Place VLSI Architecture for Viterbi Algorithm.
J. VLSI Signal Process., 2003

An efficient pipelined FFT architecture.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

Design of soft-output Viterbi decoders with hybrid trace-back processing.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2000
A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder.
IEEE J. Solid State Circuits, 2000

1999
Low-power bit-serial Viterbi decoder for next generation wide-band CDMA systems.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systems.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998
Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units.
J. VLSI Signal Process., 1998

High-performance digit-serial complex-number multiplier-accumulator.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997
Design and Implementation of Low-Power Digit-Serial Multipliers.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Loop-List Scheduling for Heterogeneous Functional Units.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996


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