Jaroslav Borecký

According to our database, Jaroslav Borecký authored at least 10 papers between 2009 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

Evaluation of the Medium-sized Neural Network using Approximative Computations on Zynq FPGA.

Miroslav Skrbek, Pavel Kubalík, Martin Kohlík, Jaroslav Borecký, Robert Hülle

Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023

2020

Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing.

Jaroslav Borecký, Robert Hülle, Petr Fiser

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2017

Parity driven reconfigurable duplex system.

Jaroslav Borecký, Martin Kohlík, Hana Kubátová

Microprocess. Microsystems, 2017

2016

Enhanced Duplication Method with TMR-Like Masking Abilities.

Jaroslav Borecký, Martin Kohlík, Pavel Vit, Hana Kubátová

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Parity Waterfall method.

Jaroslav Borecký, Martin Kohlík, Hana Kubátová

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2014

Fault Tolerant Duplex System with High Availability for Practical Applications.

Pavel Vit, Jaroslav Borecký, Martin Kohlík, Hana Kubátová

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2012

Miscellaneous Types of Partial Duplication Modifications for Availability Improvements.

Martin Kohlík, Jaroslav Borecký, Hana Kubátová

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011

Fault Models Usability Study for On-line Tested FPGA.

Jaroslav Borecký, Martin Kohlík, Pavel Kubalík, Hana Kubátová

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

Faults Coverage Improvement Based on Fault Simulation and Partial Duplication.

Jaroslav Borecký, Martin Kohlík, Hana Kubátová, Pavel Kubalík

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Reliable Railway Station System Based on Regular Structure Implemented in FPGA.

Jaroslav Borecký, Pavel Kubalík, Hana Kubátová

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009