Pavel Kubalík

According to our database, Pavel Kubalík authored at least 27 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

Evaluation of the Medium-sized Neural Network using Approximative Computations on Zynq FPGA.

Miroslav Skrbek, Pavel Kubalík, Martin Kohlík, Jaroslav Borecký, Robert Hülle

Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023

2022

Approximate arithmetic for modern neural networks and FPGAs.

Miroslav Skrbek, Pavel Kubalík

Proceedings of the 11th Mediterranean Conference on Embedded Computing, 2022

Feasibility of a Neural Network with Linearly Approximated Functions on Zynq FPGA.

Miroslav Skrbek, Pavel Kubalík

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2020

An In-Sight Into How Compression Dictionary Architecture Can Affect the Overall Performance in FPGAs.

Matej Bartík, Tomás Benes, Pavel Kubalík

IEEE Access, 2020

Low Power Wireless Data Transfer for Internet of Things: GSM Network Measuring Results.

Vojtech Procházka, Pavel Kubalík, Hana Kubátová

Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

2019

High Throughput and Low Latency LZ4 Compressor on FPGA.

Tomás Benes, Matej Bartík, Pavel Kubalík

Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

Ultra High Resolution Jitter Measurement Method for Ethernet Based Networks.

Karel Hynek, Tomás Benes, Matej Bartik, Pavel Kubalík

Proceedings of the IEEE 9th Annual Computing and Communication Workshop and Conference, 2019

Design of a High-Throughput Match Search Unit for Lossless Compression Algorithms.

Matej Bartik, Tomás Benes, Pavel Kubalík

Proceedings of the IEEE 9th Annual Computing and Communication Workshop and Conference, 2019

2018

Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary: (Abstract Only).

Matej Bartík, Sven Ubik, Pavel Kubalík, Tomás Benes

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017

Design of a Residue Number System Based Linear System Solver in Hardware.

Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický

J. Signal Process. Syst., 2017

2016

A novel and efficient method to initialize FPGA embedded memory content in asymptotically constant time.

Matej Bartik, Sven Ubik, Pavel Kubalík

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

2015

LZ4 compression algorithm on FPGA.

Matej Bartik, Sven Ubik, Pavel Kubalík

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014

System on chip design of a linear system solver.

Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický

Proceedings of the 2014 International Symposium on System-on-Chip, 2014

An ASIC linear congruence solver synthesized with three cell libraries.

Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013

Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver.

Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Dedicated hardware implementation of a linear congruence solver in FPGA.

Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

Fault Models Usability Study for On-line Tested FPGA.

Jaroslav Borecký, Martin Kohlík, Pavel Kubalík, Hana Kubátová

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

Faults Coverage Improvement Based on Fault Simulation and Partial Duplication.

Jaroslav Borecký, Martin Kohlík, Hana Kubátová, Pavel Kubalík

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Reliable Railway Station System Based on Regular Structure Implemented in FPGA.

Jaroslav Borecký, Pavel Kubalík, Hana Kubátová

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

Dependable design technique for system-on-chip.

Pavel Kubalík, Hana Kubátová

J. Syst. Archit., 2008

Experimental SEU Impact on Digital Design Implemented in FPGAs.

Jirí Kvasnicka, Pavel Kubalík, Hana Kubátová

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA.

Petr Fiser, Pavel Kubalík, Hana Kubátová

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System.

Pavel Kubalík, Jirí Kvasnicka, Hana Kubátová

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Fault Tolerant System Design Method Based on Self-Checking Circuits.

Pavel Kubalík, Petr Fiser, Hana Kubátová

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Dependable Design for FPGA Based on Duplex System and Reconfiguration.

Pavel Kubalík, Radek Dobias, Hana Kubátová

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Dependability Computation for Fault Tolerant Reconfigurable Duplex System.

Pavel Kubalík, Radek Dobias, Hana Kubátová

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005

Dependability computations for fault-tolerant system based on FPGA.

Radek Dobias, Pavel Kubalík, Hana Kubátová

Proceedings of the 12th IEEE International Conference on Electronics, 2005