Javier de San Pedro

Orcid: 0000-0002-9535-8982

According to our database1, Javier de San Pedro authored at least 11 papers between 2012 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2017
Structure discovery techniques for circuit design and process model visualization.
PhD thesis, 2017

2016
Mining structured petri nets for the visualization of process behavior.
Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016

Discovering Duplicate Tasks in Transition Systems for the Simplification of Process Models.
Proceedings of the Business Process Management - 14th International Conference, 2016

Specification Mining for Asynchronous Controllers.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015
Log-Based Simplification of Process Models.
Proceedings of the Business Process Management - 13th International Conference, 2015

2014
A hierarchical approach for generating regular floorplans.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013
Architectural Exploration of Large-Scale Hierarchical Chip Multiprocessors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Physical planning for the architectural exploration of large-scale chip multiprocessors.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Physical-aware system-level design for tiled hierarchical chip multiprocessors.
Proceedings of the International Symposium on Physical Design, 2013

2012
Integrating formal verification in an online judge for e-Learning logic circuit design.
Proceedings of the 43rd ACM technical symposium on Computer science education, 2012

Analytical Performance Modeling of Hierarchical Interconnect Fabrics.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012


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