Javier Granizo

Orcid: 0000-0002-0857-862X

According to our database1, Javier Granizo authored at least 8 papers between 2022 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2025
Second-Order VCO-ADC Architecture With Low-Area and High Dynamic Range Using Internal Binary Encoding.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2025

Analysis of Clock Jitter in VCO-ADCs Under Presence of Mismatch and Blocking Signals.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
A Second-Order Audio VCO-ADC with 103-dB-A Dynamic Range and Binary-Weighted Internal Architecture.
CoRR, 2024

A Scalable and PVT Invariant Spiking Neuron Using Asynchronous CMOS Logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
A VCO-ADC Linearized by a Capacitive Frequency-to-Current Converter.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

A CMOS LIF neuron based on a charge-powered oscillator with time-domain threshold logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Validation of a CMOS SNN network based on a time-domain threshold neuron circuit achieving 114.90 pJ/inference on MNIST.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
A 55nm CMOS Linearized Oscillator for Audio VCO-ADCs achieving 78dBA of SNDR with $153\mu \mathrm{W}$.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022


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