Luis Hernández

Orcid: 0000-0002-0433-2032

Affiliations:
  • Carlos III University, Electronic Technology Department, Madrid, Spain


According to our database1, Luis Hernández authored at least 72 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
A VCO-Based ADC With Inherent Mixing Capability and Local Oscillator Suppression in 55-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

A VCO-ADC Linearized by a Capacitive Frequency-to-Current Converter.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

A Gray-Encoded Ring Oscillator for Efficient Frequency-to-Digital Conversion in VCO-Based ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

A Different View of Sigma-Delta Modulators Under the Lens of Pulse Frequency Modulation.
CoRR, 2023

Analysis of in-band Spurious Tones of VCO-based Analog Filters and Mitigation Techniques.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A CMOS LIF neuron based on a charge-powered oscillator with time-domain threshold logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Validation of a CMOS SNN network based on a time-domain threshold neuron circuit achieving 114.90 pJ/inference on MNIST.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
Optimal reconfiguration instant in ΣΔ Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A maximally-digital VCO-ADC with inherent mixing input capability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Phase-Encoded Voice Features Extraction Circuit Using Digital Mixers and Analog Filters based on Ring Oscillators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 55nm CMOS Linearized Oscillator for Audio VCO-ADCs achieving 78dBA of SNDR with $153\mu \mathrm{W}$.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
A 73dB-A Audio VCO-ADC Based on a Maximum Length Sequence Generator in 130nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
Low Power Phase-Encoded MAC Accelerator for Smart Sensors with VCO-based ADCs.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A Model of Continuous-Time Sigma Delta Modulation Based on Pulse Frequency Encoding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

VCO-ADC Linearization by Switched Capacitor Frequency-to-Current Conversion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A Pulse Frequency Modulation VCO-ADC in 40 nm.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Clock Jitter Analysis of Continuous-Time ΣΔ Modulators Based on a Relative Time-Base Projection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A VCO-Based CMOS Readout Circuit for Capacitive MEMS Microphones.
Sensors, 2019

VCO-based Feature Extraction Architecture for Low Power Speech Recognition Applications.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

VCO-ADCs with a Quadrature Band-Pass Noise-Transfer-Function.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Continuous Time Sigma-Delta Modulator with VCO-based integrators and optimized NTF zeros.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Resolution Enhancement of VCO-based ADCs by Passive Interpolation and Phase Injection.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2018
A Pulse Frequency Modulation Interpretation of VCOs Enabling VCO-ADC Architectures With Extended Noise Shaping.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

SNDR Limits of Oscillator-Based Sensor Readout Circuits.
Sensors, 2018

0.04-mm<sup>2</sup> 103-dB-A Dynamic Range Second-Order VCO-Based Audio ΣΔ ADC in 0.13-µm CMOS.
IEEE J. Solid State Circuits, 2018

VCO-ADC Resolution Enhancement Using Maximum Length Sequences.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Why and How VCO-based ADCs can improve instrumentation applications.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Optimal NTF zero placement in MASH VCO-ADCs with higher order noise shaping.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A Highly Linear Ring Oscillator for VCO-based ADCs in 65-nm CMOS.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Noise-shaping time-interleaved ADC based on a single ring oscillator and a sampling array.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016
Frequency-encoded integrators applied to filtering and sigma-delta modulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Analytical Evaluation of VCO-ADC Quantization Noise Spectrum Using Pulse Frequency Modulation.
IEEE Signal Process. Lett., 2015

A noise coupled ΣΔ architecture using a Non Uniform Quantizer.
Proceedings of the Nordic Circuits and Systems Conference, 2015

Spectral analysis of multibit VCO-ADCs and PFM-ADCs with sinusoidal inputs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A MEMS microphone interface based on a CMOS LC oscillator and a digital sigma-delta modulator.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
A low power and low distortion VCO based ADC using a pulse frequency modulator.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A time-encoding CMOS capacitive sensor readout circuit with flicker noise reduction.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A 0.03mm<sup>2</sup>, 40nm CMOS 1.5GS/s all-digital complementary PWM-GRO.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

A digitally corrected ADC using a passive pulse frequency modulator.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
A multi-stage and time-based continuous time ΣΔ Architecture using a Gated Ring Oscillator.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A distortion corrected passive RC noise shaping ADC for biomedical applications.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Analysis of VCO based noise shaping ADCs linearized by PWM modulation.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
A 7 mW 20 MHz BW Time-Encoding Oversampling Converter Implemented in a 0.08 mm <sup>2</sup> 65 nm CMOS Circuit.
IEEE J. Solid State Circuits, 2011

1.4V 13μW 83dB DR CT-ΣΔ modulator with Dual-Slope quantizer and PWM DAC for biopotential signal acquisition.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
Continuous Time Cascade Sigma Delta Modulator without digital cancellation filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Exploiting time resolution in nanometre CMOS data converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A time encoded decimation filter for noise shaped power DACs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 0.08 mm2, 7mW Time-Encoding Oversampling Converter with 10 bits and 20MHz BW in 65nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
A 1.2-MHz 10-bit Continuous-Time Sigma-Delta ADC Using a Time Encoding Quantizer.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 0.1 mm<sup>2</sup>, Wide Bandwidth Continuous-Time ΔΣ ADC Based on a Time Encoding Quantizer in 0.13 µm CMOS.
IEEE J. Solid State Circuits, 2009

Second-order multi-bit ΣΔ ADC using a Pulse-Width Modulated DAC and an integrating quantizer.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Analog-to-Digital Conversion Using Noise Shaping and Time Encoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A subsampling bandpass SigmaDelta modulator with lumped and distributed resonators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A one-path quadrature bandpass ΣΔ modulator based on distributed resonators at 25 MHz IF.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

An A/D converter based on pulse width modulation and the walsh-hadamard transform.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Resolution enhancement of sigma-delta modulators using a tracking digital filter.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
A Subsampling Quadrature Σ∆ Modulator Based on Distributed Resonators for Use in Radio Receiver.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

2006
Clock jitter compensation for current steering DACs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Spectral shaping of clock jitter errors for continuous time sigma-delta modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A continuous-time band-pass Sigma Delta modulator implemented in 0.35µm BiCMOS using transmission lines.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 2-2 Discrete Time Cascaded ΣΔ Modulator With NTF Zero Using Interstage Feedback.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Design of Cascaded Continuous-Time Sigma-Delta Modulators.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Analog to digital conversion using a Pulse Width Modulator and an irregular sampling decoder.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Synthesis of sigma delta modulators employing continuous time delays.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution.
IEEE J. Solid State Circuits, 2004

Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A jitter insensitive continuous-time ΣΔ modulator using transmission lines.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Continuous time sigma-delta modulators with transmission line resonators and improved jitter and excess loop delay performance.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13μm CMOS.
Proceedings of the ESSCIRC 2003, 2003

2002
A superregenerative receiver for phase and frequency modulated carriers.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

1999
A continuous-time noise-shaping modulator for logarithmic A/D conversion.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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