Jay H. O'Neill

According to our database, Jay H. O'Neill authored at least 4 papers between 1993 and 2002.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2002

A CMOS low-power multiple 2.5-3.125-Gb/s serial link macrocellfor high IO bandwidth network ICs.

Fuji Yang, Jay H. O'Neill, David Inglis, Joseph H. Othmer

IEEE J. Solid State Circuits, 2002

1999

A single-chip 1.6 billion 16-b MAC/s multiprocessor DSP.

Bryan D. Ackland, A. Anesko, D. Brinthaupt, S. J. Daubert, Asawaree Kalavade, J. Knobloch, E. Micca, M. Moturi, Chris J. Nicol, Jay H. O'Neill, Joe Othmer, Eduard Sackinger, Kanwar Jit Singh, J. Sweet, C. J. Terman, Joseph Williams

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1997

A low-power 128-tap digital adaptive equalizer for broadband modems.

Chris J. Nicol, Patrik Larsson, Kamran Azadet, Jay H. O'Neill

IEEE J. Solid State Circuits, 1997

1993

A 200 MHz CMOS broad-band switching chip.

Jay H. O'Neill, Bryan D. Ackland, Sailesh K. Rao, Mehdi Hatamian

IEEE J. Solid State Circuits, March, 1993