Patrik Larsson

According to our database, Patrik Larsson authored at least 17 papers between 1992 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Accelerating container-based deep learning hyperparameter optimization workloads.

Rui Liu, David Wong, Dave Lange, Patrik Larsson, Vinay Jethava, Qing Zheng

Proceedings of the DEEM '22: Proceedings of the Sixth Workshop on Data Management for End-To-End Machine Learning Philadelphia, 2022

2018

Cognitive Ability Evaluation using Virtual Reality and Eye Tracking.

Julius Pettersson, Anton Albo, Johan Eriksson, Patrik Larsson, Kertsin Watson Falkman, Petter Falkman

Proceedings of the IEEE International Conference on Computational Intelligence and Virtual Environments for Measurement Systems and Applications, 2018

2001

Measurements and analysis of PLL jitter caused by digital switching noise.

Patrik Larsson

IEEE J. Solid State Circuits, 2001

1999

A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability.

Patrik Larsson

IEEE J. Solid State Circuits, 1999

Power supply noise in future IC's: a crystal ball reading.

Patrik Larsson

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998

Reconfigurable hardware for efficient implementation of programmable FIR filters.

Tracy C. Denk, Chris J. Nicol, Patrik Larsson, Kamran Azadet

Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

1997

A low-power 128-tap digital adaptive equalizer for broadband modems.

Chris J. Nicol, Patrik Larsson, Kamran Azadet, Jay H. O'Neill

IEEE J. Solid State Circuits, 1997

Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance.

Patrik Larsson

IEEE J. Solid State Circuits, 1997

Low power multiplication for FIR filters.

Chris J. Nicol, Patrik Larsson

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

1996

High-speed architecture for a programmable frequency divider and a dual-modulus prescaler.

Patrik Larsson

IEEE J. Solid State Circuits, 1996

Transition reduction in carry-save adder trees.

Patrik Larsson, Chris J. Nicol

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995

Fast and Accurate Event Driven Simulation of Partly Analog Phase-Locked Loops.

Patrik Larsson

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Skew Safety and Logic Flexibility in a True Single Phase Clocked System.

Patrik Larsson

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A Wide-Range Progammable High-Speed CMOS Frequency Divider.

Patrik Larsson

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

Impact of clock slope on true single phase clocked (TSPC) CMOS circuits.

Patrik Larsson, Christer Svensson

IEEE J. Solid State Circuits, June, 1994

Noise in digital dynamic CMOS circuits.

Patrik Larsson, Christer Svensson

IEEE J. Solid State Circuits, June, 1994

1992

A Distributed Neural Network Architecture for Hexapod Robot Locomotion.

Randall D. Beer, Hillel J. Chiel, Roger D. Quinn, Kenneth S. Espenschied, Patrik Larsson

Neural Comput., 1992