Jay Pathak
Orcid: 0000-0003-2387-6809
According to our database1,
Jay Pathak
authored at least 20 papers
between 2017 and 2023.
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Bibliography
2023
2022
On the Geometry Transferability of the Hybrid Iterative Numerical Solver for Differential Equations.
CoRR, 2022
A Hybrid Iterative Numerical Transferable Solver (HINTS) for PDEs Based on Deep Operator Network and Relaxation Methods.
CoRR, 2022
A composable machine-learning approach for steady-state simulations on high-resolution grids.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022
2021
Algorithmically-consistent deep learning frameworks for structural topology optimization.
Eng. Appl. Artif. Intell., 2021
A composable autoencoder-based iterative algorithm for accelerating numerical simulations.
CoRR, 2021
CoRR, 2021
ActivationNet: Representation learning to predict contact quality of interacting 3-D surfaces in engineering designs.
CoRR, 2021
Analysis of Standard Cells performance for In0.53Ga0.47As FinFET with underlap fin length for High Speed Applications.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021
2020
Solving Inverse Problems in Steady State Navier-Stokes Equations using Deep Neural Networks.
CoRR, 2020
An unsupervised learning approach to solving heat equations on chip based on Auto Encoder and Image Gradient.
CoRR, 2020
DiscretizationNet: A Machine-Learning based solver for Navier-Stokes Equations using Finite Volume Discretization.
CoRR, 2020
2019
Assessment of interface traps in In<sub>0.53</sub>Ga<sub>0.47</sub>As FinFET with gate-to-source/drain underlap for sub-14 nm technology node to impede short channel effect.
IET Circuits Devices Syst., 2019
Stability Analysis of SRAM Designed Using In0.53Ga0.47As nFinFET with Underlap Region.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
2017
Investigation of TCADs Models for Characterization of Sub 16 nm In _0.53 Ga _0.47 As FinFET.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017