Jayabrata Ghosh-Dastidar

According to our database1, Jayabrata Ghosh-Dastidar authored at least 9 papers between 1998 and 2003.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2003
An efficient test vector compression scheme using selective Huffman coding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2001
On Diagnosing Path Delay Faults in an At-Speed Environment.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Diagnosing resistive bridges using adaptive techniques.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999
Scan Vector Compression/Decompression Using Statistical Coding.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Adaptive Techniques for Improving Delay Fault Diagnosis.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Fault diagnosis in scan-based BIST using both time and space information.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
A Systematic Approach for Diagnosing Multiple Delay Faults.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998


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