Nur A. Touba

According to our database, Nur A. Touba authored at least 155 papers between 1994 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Highly Efficient Layered Syndrome-based Double Error Correction Utilizing Current Summing in RRAM Cells to Simplify Decoder.

Shruti Dutta, Sai Charan Rachamadugu Chinni, Abhishek Das, Nur A. Touba

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2022

CEnT: An Efficient Architecture to Eliminate Intra-Array Write Disturbance in PCM.

Muhammad Imran, Taehyun Kwon, Nur A. Touba, Joon-Sung Yang

IEEE Trans. Computers, 2022

2020

A New Class of Single Burst Error Correcting Codes with Parallel Decoding.

Abhishek Das, Nur A. Touba

IEEE Trans. Computers, 2020

Selective Checksum based On-line Error Correction for RRAM based Matrix Operations.

Abhishek Das, Nur A. Touba

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

2019

Layered-ECC: A Class of Double Error Correcting Codes for High Density Memory Systems.

Abhishek Das, Nur A. Touba

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

A Graph Theory Approach towards IJTAG Security via Controlled Scan Chain Isolation.

Abhishek Das, Nur A. Touba

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Online Correction of Hard Errors and Soft Errors via One-Step Decodable OLS Codes for Emerging Last Level Caches.

Abhishek Das, Nur A. Touba

Proceedings of the IEEE Latin American Test Symposium, 2019

2018

Systematic b-adjacent symbol error correcting reed-solomon codes with parallel decoding.

Abhishek Das, Nur A. Touba

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Low Complexity Burst Error Correcting Codes to Correct MBUs in SRAMs.

Abhishek Das, Nur A. Touba

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Efficient Non-Binary Hamming Codes for Limited Magnitude Errors in MLC PCMs.

Abhishek Das, Nur A. Touba

Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

2017

Enhancing Test Compression With Dependency Analysis for Multiple Expansion Ratios.

Taehee Lee, Nur A. Touba, Joon-Sung Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC.

Hyunseung Han, Nur A. Touba, Joon-Sung Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Limited Magnitude Error Correction Using OLS Codes for Memories with Multilevel Cells.

Abhishek Das, Nur A. Touba

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Improving test compression with multiple-polynomial LFSRs.

Yu-Wei Lee, Nur A. Touba

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Computing with obfuscated data in arbitrary logic circuits via noise insertion and cancellation.

Yu-Wei Lee, Nur A. Touba

Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017

2016

Enhancing Superset X-Canceling Method With Relaxed Constraints on Fault Observation.

Joon-Sung Yang, Jinsuk Chung, Nur A. Touba

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Using symbolic canceling to improve diagnosis from compacted response.

Kamran Saleem, Nur A. Touba

Proceedings of the 2016 IEEE International Test Conference, 2016

Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning.

Jin-Hyun Kang, Nur A. Touba, Joon-Sung Yang

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Improving logic obfuscation via logic cone analysis.

Yu-Wei Lee, Nur A. Touba

Proceedings of the 16th Latin-American Test Symposium, 2015

Compacting output responses containing unknowns using an embedded processor.

Kamran Saleem, Sreenivaas S. Muthyala, Nur A. Touba

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Improving X-tolerant combinational output compaction via input rotation.

Asad Amin Bawa, Nur A. Touba

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014

Reducing Cost of Yield Enhancement in 3-D Stacked Memories Via Asymmetric Layer Repair Capability.

Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba

IEEE Trans. Very Large Scale Integr. Syst., 2014

Utilizing ATE Vector Repeat With Linear Decompressor for Test Vector Compression.

Joon-Sung Yang, Jinkyu Lee, Nur A. Touba

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs.

Sreenivaas S. Muthyala, Nur A. Touba

Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

Reducing test time for 3D-ICs by improved utilization of test elevators.

Sreenivaas S. Muthyala, Nur A. Touba

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Improving test compression with scan feedforward techniques.

Sreenivaas S. Muthyala, Nur A. Touba

Proceedings of the 2014 International Test Conference, 2014

2013

Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug.

Joon-Sung Yang, Nur A. Touba

IEEE Trans. Very Large Scale Integr. Syst., 2013

SOC test compression scheme using sequential linear decompressors with retained free variables.

Sreenivaas S. Muthyala, Nur A. Touba

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes.

Pedro Reviriego, Shih-Fu Liu, Juan Antonio Maestro, S. Lee, Nur A. Touba, Rudrajit Datta

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Unified 3D test architecture for variable test data bandwidth across pre-bond, partial stack, and post-bond test.

Yu-Wei Lee, Nur A. Touba

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Efficient compression of x-masking control data via dynamic channel allocation.

Asad Amin Bawa, Muhammad Tauseef Rab, Nur A. Touba

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012

X-Canceling MISR Architectures for Output Response Compaction With Unknown Values.

Joon-Sung Yang, Nur A. Touba

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis.

Joon-Sung Yang, Nur A. Touba

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops.

Joon-Sung Yang, Nur A. Touba, Benoit Nadeau-Dostie

IEEE Trans. Computers, 2012

Exploiting X-correlation in output compression via superset X-canceling.

Jinsuk Chung, Nur A. Touba

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Using asymmetric layer repair capability to reduce the cost of yield enhancement in 3D stacked memories.

Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Improving test compression by retaining non-pivot free variables in sequential linear decompressors.

Sreenivaas S. Muthyala, Nur A. Touba

Proceedings of the 2012 IEEE International Test Conference, 2012

Implementing defect tolerance in 3D-ICs by exploiting degrees of freedom in assembly.

Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Using partial masking in X-chains to increase output compaction for an X-canceling MISR.

Asad Amin Bawa, Muhammad Tauseef Rab, Nur A. Touba

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011

Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories.

Rudrajit Datta, Nur A. Touba

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Generating Burst-Error Correcting Codes from Orthogonal Latin Square Codes - A Graph Theoretic Approach.

Rudrajit Datta, Nur A. Touba

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

X-Stacking - A Method for Reducing Control Data for Output Compaction.

Rudrajit Datta, Nur A. Touba

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010

Correlation-Based Rectangular Encoding.

Jinkyu Lee, Nur A. Touba

IEEE Trans. Very Large Scale Integr. Syst., 2010

CSER: BISER-based concurrent soft-error resilience.

Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Post-manufacturing ECC customization based on Orthogonal Latin Square codes and its application to ultra-low power caches.

Rudrajit Datta, Nur A. Touba

Proceedings of the 2011 IEEE International Test Conference, 2010

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains.

Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, FeiFei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009

Automated Selection of Signals to Observe for Efficient Silicon Debug.

Joon-Sung Yang, Nur A. Touba

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Exploiting Unused Spare Columns to Improve Memory ECC.

Rudrajit Datta, Nur A. Touba

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

An industrial case study for X-canceling MISR.

Joon-Sung Yang, Nur A. Touba, Shih-Yu Yang, T. M. Mak

Proceedings of the 2009 IEEE International Test Conference, 2009

Test point insertion using functional flip-flops to drive control points.

Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba

Proceedings of the 2009 IEEE International Test Conference, 2009

Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points.

Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Improving Memory Repair by Selective Row Partitioning.

Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

Guest Editorial.

Nur A. Touba, Adelio Salsano, Minsu Choi

J. Electron. Test., 2008

ITC 2008 Highlights.

Nur A. Touba

IEEE Des. Test Comput., 2008

Guest Editors' Introduction: Progress in Test Compression.

Scott Davidson, Nur A. Touba

IEEE Des. Test Comput., 2008

Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture.

Joon-Sung Yang, Nur A. Touba

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation.

Ritesh Garg, Richard Putman, Nur A. Touba

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Enhancing Silicon Debug via Periodic Monitoring.

Joon-Sung Yang, Nur A. Touba

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007

LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test.

Jinkyu Lee, Nur A. Touba

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Relationship Between Entropy and Test Data Compression.

Kedarnath J. Balakrishnan, Nur A. Touba

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression.

Richard Putman, Nur A. Touba

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code.

Avijit Dutta, Nur A. Touba

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

X-canceling MISR - An X-tolerant methodology for compacting output responses with unknowns using a MISR.

Nur A. Touba

Proceedings of the 2007 IEEE International Test Conference, 2007

Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code.

Avijit Dutta, Nur A. Touba

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006

Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits.

Eric W. MacDonald, Nur A. Touba

IEEE Trans. Very Large Scale Integr. Syst., 2006

Improving Linear Test Data Compression.

Kedarnath J. Balakrishnan, Nur A. Touba

IEEE Trans. Very Large Scale Integr. Syst., 2006

Survey of Test Vector Compression Techniques.

Nur A. Touba

IEEE Des. Test Comput., 2006

Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding.

Jinkyu Lee, Nur A. Touba

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Iterative OPDD Based Signal Probability Calculation.

Avijit Dutta, Nur A. Touba

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Using Limited Dependence Sequential Expansion for Decompressing Test Vectors.

Avijit Dutta, Nur A. Touba

Proceedings of the 2006 IEEE International Test Conference, 2006

Synthesis of Efficient Linear Test Pattern Generators.

Avijit Dutta, Nur A. Touba

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition.

Jinkyu Lee, Nur A. Touba

Proceedings of the 15th Asian Test Symposium, 2006

2005

Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits.

Shalini Ghosh, Sugato Basu, Nur A. Touba

J. Low Power Electron., 2005

Synthesis of Low Power CED Circuits Based on Parity Codes.

Shalini Ghosh, Sugato Basu, Nur A. Touba

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Methods for improving test compression.

Nur A. Touba

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Synthesis of nonintrusive concurrent error detection using an even error detecting function.

Avijit Dutta, Nur A. Touba

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier.

Avijit Dutta, Terence Rodrigues, Nur A. Touba

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Using Statistical Transformations to Improve Compression for Linear Decompressors.

Samuel I. Ward, Chris Schattauer, Nur A. Touba

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Low Power BIST Based on Scan Partitioning.

Jinkyu Lee, Nur A. Touba

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination.

Kedarnath J. Balakrishnan, Nur A. Touba

Proceedings of the 2005 Design, 2005

Compressing Functional Tests for Microprocessors.

Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Lowering power consumption in concurrent checkers via input ordering.

Kartik Mohanram, Nur A. Touba

IEEE Trans. Very Large Scale Integr. Syst., 2004

Test data compression technique for embedded cores using virtual scan chains.

Abhijit Jas, Bahram Pouya, Nur A. Touba

IEEE Trans. Very Large Scale Integr. Syst., 2004

Weighted pseudorandom hybrid BIST.

Abhijit Jas, C. V. Krishna, Nur A. Touba

IEEE Trans. Very Large Scale Integr. Syst., 2004

Achieving high encoding efficiency with partial dynamic LFSR reseeding.

C. V. Krishna, Abhijit Jas, Nur A. Touba

ACM Trans. Design Autom. Electr. Syst., 2004

Matrix-based software test data decompression for systems-on-a-chip.

Kedarnath J. Balakrishnan, Nur A. Touba

J. Syst. Archit., 2004

3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme.

C. V. Krishna, Nur A. Touba

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Reducing Power Consumption in Memory ECC Checkers.

Shalini Ghosh, Nur A. Touba, Sugato Basu

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion.

Kedarnath J. Balakrishnan, Nur A. Touba

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Low Power Test Data Compression Based on LFSR Reseeding.

Jinkyu Lee, Nur A. Touba

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Low-power weighted pseudo-random BIST using special scan cells.

Shalini Ghosh, Eric W. MacDonald, Sugato Basu, Nur A. Touba

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Relating entropy theory to test data compression.

Kedarnath J. Balakrishnan, Nur A. Touba

Proceedings of the 9th European Test Symposium, 2004

2003

Test data compression using dictionaries with selective entries and fixed-length indices.

Lei Li, Krishnendu Chakrabarty, Nur A. Touba

ACM Trans. Design Autom. Electr. Syst., 2003

An efficient test vector compression scheme using selective Huffman coding.

Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses.

Kartik Mohanram, Nur A. Touba

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Deterministic Test Vector Decompression in Software Using Linear Operations.

Kedarnath J. Balakrishnan, Nur A. Touba

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits.

Kartik Mohanram, Nur A. Touba

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering.

Shalini Ghosh, Sugato Basu, Nur A. Touba

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits.

Kartik Mohanram, Egor S. Sogomonyan, Michael Gössel, Nur A. Touba

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Adjustable Width Linear Combinational Scan Vector Decompression.

C. V. Krishna, Nur A. Touba

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits.

Kartik Mohanram, Nur A. Touba

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Hybrid BIST Using an Incrementally Guided LFSR.

C. V. Krishna, Nur A. Touba

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Scan-Based BIST Diagnosis Using an Embedded Processor.

Kedarnath J. Balakrishnan, Nur A. Touba

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002

Circular BIST with state skipping.

Nur A. Touba

IEEE Trans. Very Large Scale Integr. Syst., 2002

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor.

Abhijit Jas, Nur A. Touba

J. Electron. Test., 2002

Controlling Peak Power During Scan Testing.

Ranganathan Sankaralingam, Nur A. Touba

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Very Low Voltage Testing of SOI Integrated Circuits.

Eric W. MacDonald, Nur A. Touba

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression.

C. V. Krishna, Nur A. Touba

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL.

Kartik Mohanram, C. V. Krishna, Nur A. Touba

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Inserting Test Points to Control Peak Power During Scan Testing.

Ranganathan Sankaralingam, Nur A. Touba

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Input Ordering in Concurrent Checkers to Reduce Power Consumption.

Kartik Mohanram, Nur A. Touba

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Matrix-Based Test Vector Decompression Using an Embedded Processor.

Kedarnath J. Balakrishnan, Nur A. Touba

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Reducing Test Power During Test Using Programmable Scan Chain Disable.

Ranganathan Sankaralingam, Nur A. Touba

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001

Bit-fixing in pseudorandom sequences for scan BIST.

Nur A. Touba, Edward J. McCluskey

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Reducing Power Dissipation during Test Using Scan Chain Disable.

Ranganathan Sankaralingam, Nur A. Touba, Bahram Pouya

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme.

Abhijit Jas, C. V. Krishna, Nur A. Touba

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Test vector encoding using partial LFSR reseeding.

C. V. Krishna, Abhijit Jas, Nur A. Touba

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability.

Jayabrata Ghosh-Dastidar, Nur A. Touba

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000

Static Compaction Techniques to Control Scan Vector Power Dissipation.

Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Virtual Scan Chains: A Means for Reducing Scan Length in Cores.

Abhijit Jas, Bahram Pouya, Nur A. Touba

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains.

Jayabrata Ghosh-Dastidar, Nur A. Touba

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Reducing test data volume using external/LBIST hybrid test patterns.

Debaleena Das, Nur A. Touba

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes.

Debaleena Das, Nur A. Touba, Markus Seuring, Michael Gössel

Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

Diagnosing resistive bridges using adaptive techniques.

Jayabrata Ghosh-Dastidar, Nur A. Touba

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

Testing domino circuits in SOI technology.

Eric W. MacDonald, Nur A. Touba

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

RP-SYN: synthesis of random pattern testable circuits with test point insertion.

Nur A. Touba, Edward J. McCluskey

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes.

Debaleena Das, Nur A. Touba

J. Electron. Test., 1999

Scan Vector Compression/Decompression Using Statistical Coding.

Abhijit Jas, Jayabrata Ghosh-Dastidar, Nur A. Touba

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Adaptive Techniques for Improving Delay Fault Diagnosis.

Jayabrata Ghosh-Dastidar, Nur A. Touba

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits.

Debaleena Das, Nur A. Touba

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems.

Debaleena Das, Nur A. Touba

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Delay testing of SOI circuits: Challenges with the history effect.

Eric W. MacDonald, Nur A. Touba

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Fault diagnosis in scan-based BIST using both time and space information.

Jayabrata Ghosh-Dastidar, Debaleena Das, Nur A. Touba

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Configuration self-test in FPGA-based reconfigurable systems.

W. Quddus, Abhijit Jas, Nur A. Touba

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Observing test response of embedded cores through surrounding logic.

P. K. Jaini, Nur A. Touba

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip.

Abhijit Jas, Nur A. Touba

Proceedings of the IEEE International Conference On Computer Design, 1999

An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets.

Abhijit Jas, Kartik Mohanram, Nur A. Touba

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

Synthesis of Zero-Aliasing Elementary-Tree Space Compactors.

Bahram Pouya, Nur A. Touba

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

BETSY: synthesizing circuits for a specified BIST environment.

Zhe Zhao, Bahram Pouya, Nur A. Touba

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Test vector decompression via cyclical scan chains and its application to testing core-based designs.

Abhijit Jas, Nur A. Touba

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

A Systematic Approach for Diagnosing Multiple Delay Faults.

Jayabrata Ghosh-Dastidar, Nur A. Touba

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST.

Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunderlich

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Logic synthesis of multilevel circuits with concurrent error detection.

Nur A. Touba, Edward J. McCluskey

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Using Partial Isolation Rings to Test Core-Based Designs.

Nur A. Touba, Bahram Pouya

IEEE Des. Test Comput., 1997

Testing Embedded Cores Using Partial Isolation Rings.

Nur A. Touba, Bahram Pouya

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Obtaining High Fault Coverage with Circular BIST Via State Skipping.

Nur A. Touba

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Modifying User-Defined Logic for Test Access to Embedded Cores.

Bahram Pouya, Nur A. Touba

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Pseudo-Random Pattern Testing of Bridging Faults.

Nur A. Touba, Edward J. McCluskey

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996

Applying two-pattern tests using scan-mapping.

Nur A. Touba, Edward J. McCluskey

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Test point insertion based on path tracing.

Nur A. Touba, Edward J. McCluskey

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Altering a Pseudo-Random Bit Sequence for Scan-Based BIST.

Nur A. Touba, Edward J. McCluskey

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995

Transformed pseudo-random patterns for BIST.

Nur A. Touba, Edward J. McCluskey

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST.

Nur A. Touba, Edward J. McCluskey

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994

Automated Logic Synthesis of Random-Pattern-Testable Circuits.

Nur A. Touba, Edward J. McCluskey

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection.

Nur A. Touba, Edward J. McCluskey

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994