Srikanth Venkataraman

According to our database1, Srikanth Venkataraman authored at least 63 papers between 1995 and 2019.

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Bibliography

2019
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design.
ACM Trans. Design Autom. Electr. Syst., 2019

Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Interconnect-aware tests to complement gate-exhaustive tests.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

2017
Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction.
IEEE Trans. VLSI Syst., 2017

Test Modification for Reduced Volumes of Fail Data.
ACM Trans. Design Autom. Electr. Syst., 2017

Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure.
Proceedings of the IEEE International Test Conference, 2017

2016
Diagnostic Fail Data Minimization Using an N-Cover Algorithm.
IEEE Trans. VLSI Syst., 2016

Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

A novel diagnostic test generation methodology and its application in production failure isolation.
Proceedings of the 2016 IEEE International Test Conference, 2016

A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2014
Built-in generation of functional broadside tests considering primary input constraints.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013
Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes?
Proceedings of the 18th IEEE European Test Symposium, 2013

2012
Tutorial T3: DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield.
Proceedings of the 25th International Conference on VLSI Design, 2012

2011
Logic BIST silicon debug and volume diagnosis methodology.
Proceedings of the 2011 IEEE International Test Conference, 2011

2010
Defect diagnosis based on DFM guidelines.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

2009
Automated Debug of Speed Path Failures Using Functional Tests.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Microprocessor system failures debug and fault isolation methodology.
Proceedings of the 2009 IEEE International Test Conference, 2009

2008
Diagnosis of Scan Clock Failures.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

DFM / DFT / SiliconDebug / Diagnosis.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Using Scan-Dump Values to Improve Functional-Diagnosis Methodology.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Testing for systematic defects based on DFM guidelines.
Proceedings of the 2007 IEEE International Test Conference, 2007

Quality Driven Manufacturing and SOC Designs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Making Manufacturing Work For You.
Proceedings of the 44th Design Automation Conference, 2007

2006
Extraction error modeling and automated model debugging in high-performance custom designs.
IEEE Trans. VLSI Syst., 2006

An algorithmic technique for diagnosis of faulty scan chains.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Accelerating Diagnostic Fault Simulation Using Z-diagnosis and Concurrent Equivalence Identification.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Dominance Based Analysis for Large Volume Production Fail Diagnosis.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Improving Precision Using Mixed-level Fault Diagnosis.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
Achieving higher yield through diagnosis?
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Enabling yield analysis with X-compact.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Fault Diagnosis and Fault Model Aliasing.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs.
Proceedings of the 2005 Design, 2005

2004
An Experimental Study of N-Detect Scan ATPG Patterns on a Processor.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Razor: A Tool for Post-Silicon Scan ATPG Pattern Debug and Its Application.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Diagnosis meets Physical Failure Analysis: What is needed to succeed?
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis.
Proceedings of the 2004 Design, 2004

2003
Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

2001
Diagnostic simulation of stuck-at faults in sequential circuits using compact lists.
ACM Trans. Design Autom. Electr. Syst., 2001

Poirot: Applications of a Logic Fault Diagnosis Tool.
IEEE Design & Test of Computers, 2001

On Diagnosing Path Delay Faults in an At-Speed Environment.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

A technique for fault diagnosis of defects in scan chains.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000
A Technique for Logic Fault Diagnosis of Interconnect Open Defects.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

POIROT: a logic fault diagnosis tool and its applications.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

1998
Diagnostic Simulation of Sequential Circuits Using Fault Sampling.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997
Distributed Diagnostic Simulation of Stuck-At Faults in Sequential Circuits.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Diagnosis of Bridging Faults in Sequential Circuits Using Adaptive Simulation, State Storage, and Path-Tracing.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

A deductive technique for diagnosis of bridging faults.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996
Diagnostic simulation of stuck-at faults in combinational circuits.
J. Electronic Testing, 1996

Dynamic diagnosis of sequential circuits based on stuck-at faults.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Partial Scan Design Based on Circuit State Information.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.
IEEE Trans. Computers, 1995

Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists.
Proceedings of the 32st Conference on Design Automation, 1995


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