Jayanth Thangellamudi

According to our database, Jayanth Thangellamudi authored at least 4 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Bridging RTL and Assertion Generation With Large Language Models.

Jayanth Thangellamudi, Sai Manoj Pudukotai Dinakarrao

IEEE Des. Test, June, 2026

Hardware Trojan Detection and Interpretation Using Graph Neural Networks.

Jayanth Thangellamudi, Negar Etemadyrad, Liang Zhao, Sai Manoj P. D.

Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

VeriRAG: A Knowledge Graph-Augmented RAG for Verilog and Assertion Generation.

Jayanth Thangellamudi, Raghul Saravanan, Sai Manoj Pudukotai Dinakarrao

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

3D-PLANE: A 3D-stacked DRAM-based Programmable SLM Accelerator Capable of Near-Memory and Energy-Efficient Parallel Processing.

Sathwika Bavikadi, Purab Ranjan Sutradhar, Jayanth Thangellamudi, Sai Manoj Pudukotai Dinakarrao

Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025