Raghul Saravanan

Orcid: 0000-0002-8296-2144

According to our database1, Raghul Saravanan authored at least 11 papers between 2023 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
VeriRAG: A Knowledge Graph-Augmented RAG for Verilog and Assertion Generation.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

TargetFuzz: Enabling Directed Graybox Fuzzing via SAT-Guided Seed Generation.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
Logic Solver Guided Directed Fuzzing for Hardware Designs.
CoRR, September, 2025

Intelligent Graybox Fuzzing via ATPG-Guided Seed Generation and Submodule Analysis.
CoRR, September, 2025

SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs.
CoRR, April, 2025

PROFUZZ: Directed Graybox Fuzzing via Module Selection and ATPG-Guided Seed Generation.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

2024
Accelerating Hardware Verification with Graph Models.
CoRR, 2024

The Emergence of Hardware Fuzzing: A Critical Review of its Significance.
CoRR, 2024

Exploring Coverage Metrics in Hardware Fuzzing: A Comprehensive Analysis.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

The Fuzz Odyssey: A Survey on Hardware Fuzzing Frameworks for Hardware Design Verification.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2023
Reconfigurable FET Approximate Computing-based Accelerator for Deep Learning Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023


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