Jean Jyh-Jiun Shann

According to our database1, Jean Jyh-Jiun Shann authored at least 31 papers between 1994 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2017
Translating OpenACC program for HAS environment.
Proceedings of the International Conference on Computer, 2017

2016
Translating OpenACC to LLVM IR with SPIR kernels.
Proceedings of the 15th IEEE/ACIS International Conference on Computer and Information Science, 2016

2015
Reconfigurable Custom Functional Unit Generation and Exploitation for Multiple-Issue Processors.
J. Inf. Sci. Eng., 2015

Instruction Emulation and OS Supports of a Hybrid Binary Translator for x86 Instruction Set Architecture.
Proceedings of the 2015 IEEE 12th Intl Conf on Ubiquitous Intelligence and Computing and 2015 IEEE 12th Intl Conf on Autonomic and Trusted Computing and 2015 IEEE 15th Intl Conf on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom), 2015

2014
Extended Instruction Exploration for Multiple-Issue Architectures.
ACM Trans. Embedded Comput. Syst., 2014

2013
Improving performance of JNA by using LLVM JIT compiler.
Proceedings of the 2013 IEEE/ACIS 12th International Conference on Computer and Information Science, 2013

2012
Modification and implementation of an edge-based fast intra prediction mode decision algorithm for H.264/AVC high resolution real-time systems.
J. Visual Communication and Image Representation, 2012

A predicate-aware modulo scheduling for improving resource efficiency of coarse grained reconfigurable architectures.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

2011
Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration.
J. Inf. Sci. Eng., 2011

2010
Reconfigurable custom functional unit generation and exploitation in multiple-issue processors.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

2009
Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

Methods for Precise False-Overlap Detection in Tile-Based Rendering.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

2008
Instruction Set Extension Exploration in Multiple-Issue Architecture.
Proceedings of the Design, Automation and Test in Europe, 2008

ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor.
Proceedings of the 45th Design Automation Conference, 2008

2007
Instruction Set Extension Generation with Considering Physical Constraints.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007

2006
Unique-order interpolative coding for fast querying and space-efficient indexing in information retrieval systems.
Inf. Process. Manage., 2006

Fast query evaluation through document identifier assignment for inverted file-based information retrieval systems.
Inf. Process. Manage., 2006

Design and implementation of a reconfigurable hardware for secure embedded systems.
Proceedings of the 2006 ACM Symposium on Information, Computer and Communications Security, 2006

2005
Low-Power Branch Prediction.
Proceedings of the 2005 International Conference on Computer Design, 2005

Low-Power Data Address Bus Encoding Method.
Proceedings of the 2005 International Conference on Computer Design, 2005

2004
A software/hardware cooperated stack operations folding model for Java processors.
Journal of Systems and Software, 2004

A Unique-Order Interpolative Code for Fast Querying and Space-Efficient Indexing in Information Retrieval Systems.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

2003
Compressing MIPS code by multiple operand dependencies.
ACM Trans. Embedded Comput. Syst., 2003

An Inverted File Cache for Fast Information Retrieval.
J. Inf. Sci. Eng., 2003

Inverted file compression through document identifier reassignment.
Inf. Process. Manage., 2003

2002
Design of an optimal folding mechanism for Java processors.
Microprocessors and Microsystems, 2002

Code Compression by Register Operand Dependency.
Proceedings of the 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 2002

2001
Aggressive Schduling for Memory Accesses of CISC Superscalar Microprocessors.
J. Inf. Sci. Eng., 2001

1998
An X86 Load/Store Unit with Aggressive Scheduling of Load/Store Operations.
Proceedings of the International Conference on Parallel and Distributed Systems, 1998

Decoding Unit with High Issue Rate for X86 Superscalar Microprocessors.
Proceedings of the International Conference on Parallel and Distributed Systems, 1998

1994
A Fuzzy Neural Network for Knowledge Learning.
Int. J. Neural Syst., 1994


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