Chung-Ping Chung

According to our database1, Chung-Ping Chung
  • authored at least 73 papers between 1989 and 2015.
  • has a "Dijkstra number"2 of four.

Timeline

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Bibliography

2015
Reconfigurable Custom Functional Unit Generation and Exploitation for Multiple-Issue Processors.
J. Inf. Sci. Eng., 2015

2014
Extended Instruction Exploration for Multiple-Issue Architectures.
ACM Trans. Embedded Comput. Syst., 2014

Exploiting fine-grain parallelism in the H.264 deblocking filter by operation reordering.
Future Generation Comp. Syst., 2014

2011
Load and storage balanced posting file partitioning for parallel information retrieval.
Journal of Systems and Software, 2011

Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration.
J. Inf. Sci. Eng., 2011

Tolerating Load Miss-Latency by Extending Effective Instruction Window with Low Complexity.
Proceedings of the International Conference on Parallel Processing, 2011

Set Utilization Based Dynamic Shared Cache Partitioning.
Proceedings of the 17th IEEE International Conference on Parallel and Distributed Systems, 2011

Exploiting Parallelism in the H.264 Deblocking Filter by Operation Reordering.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2011

2010
Reconfigurable custom functional unit generation and exploitation in multiple-issue processors.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

2009
Smaller Split L-1 Data Caches for Multi-core Processing Systems.
Proceedings of the 10th International Symposium on Pervasive Systems, 2009

Methods for Precise False-Overlap Detection in Tile-Based Rendering.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

A Hierarchical Primitive Lists Structure for Tile-Based Rendering.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

H-Buffer: An Efficient History-Based and Overflow Sharing Transparent Fragment Storage Method.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

Blocked-Z Test for Reducing Rasterization, Z Test and Shading Workloads.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

Dynamic Reconfigurable Shaders with Load Balancing for Embedded Graphics Processing.
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

2008
Filtering of Unnecessary Branch Predictor Lookups for Low-power Processor Architecture.
J. Inf. Sci. Eng., 2008

iAIM: An Intelligent Autonomous Instruction Memory with Branch Handling Capability.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

Instruction Set Extension Exploration in Multiple-Issue Architecture.
Proceedings of the Design, Automation and Test in Europe, 2008

ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor.
Proceedings of the 45th Design Automation Conference, 2008

Mechanism for return stack and branch history corrections under misprediction in deep pipeline design.
Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008

Early load: Hiding load latency in deep pipeline processor.
Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008

2007
Instruction Set Extension Generation with Considering Physical Constraints.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007

Selecting Heterogeneous Computation Blocks for Reconfigurable JPEG Codec Computing.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

A Run-Time Reconfigurable Fabric for 3D Texture Filtering.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Unique-order interpolative coding for fast querying and space-efficient indexing in information retrieval systems.
Inf. Process. Manage., 2006

Fast query evaluation through document identifier assignment for inverted file-based information retrieval systems.
Inf. Process. Manage., 2006

Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

2005
Designing A Disjoint Paths Interconnection Network with Fault Tolerance and Collision Solving.
The Journal of Supercomputing, 2005

A statistics-based approach to incrementally update inverted files.
Inf. Process. Manage., 2005

Low-Power Branch Prediction.
Proceedings of the 2005 International Conference on Computer Design, 2005

Low-Power Data Address Bus Encoding Method.
Proceedings of the 2005 International Conference on Computer Design, 2005

2004
A software/hardware cooperated stack operations folding model for Java processors.
Journal of Systems and Software, 2004

Code compression by register operand dependency.
Journal of Systems and Software, 2004

Branch-and-bound task allocation with task clustering-based pruning.
J. Parallel Distrib. Comput., 2004

A Unique-Order Interpolative Code for Fast Querying and Space-Efficient Indexing in Information Retrieval Systems.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

2003
Compressing MIPS code by multiple operand dependencies.
ACM Trans. Embedded Comput. Syst., 2003

Variable-size data item placement for load and storage balancing.
Journal of Systems and Software, 2003

3-Disjoint gamma interconnection networks.
Journal of Systems and Software, 2003

An Inverted File Cache for Fast Information Retrieval.
J. Inf. Sci. Eng., 2003

Inverted file compression through document identifier reassignment.
Inf. Process. Manage., 2003

A Tree-Based inverted File for Fast Ranked-Document Retrieval.
Proceedings of the International Conference on Information and Knowledge Engineering. IKE'03, June 23, 2003

A Statistics-Based Approach to Incrementally Update Inverted Files.
Proceedings of the International Conference on Information and Knowledge Engineering. IKE'03, June 23, 2003

2002
Design of an optimal folding mechanism for Java processors.
Microprocessors and Microsystems, 2002

Posting file partitioning and parallel information retrieval.
Journal of Systems and Software, 2002

An analytical POC stack operations folding for continuous and discontinuous Java bytecodes.
Journal of Systems Architecture, 2002

Design of Instruction Address Queue for High Degree X86 Superscalar Architecture.
J. Inf. Sci. Eng., 2002

Code Compression by Register Operand Dependency.
Proceedings of the 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 2002

2001
A dominance relation enhanced branch-and-bound task allocation.
Journal of Systems and Software, 2001

Fault-tolerant gamma interconnection network without backtracking.
Journal of Systems and Software, 2001

2000
Applying stack simulation for branch target buffers.
Journal of Systems and Software, 2000

Design of Instruction Stream Buffer with Trace Support for X86 Processors.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Exploiting Java Bytecode Parallelism by Enhanced POC Folding Model (Research Note).
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

1999
Reducing Memory Traffic and Accelerting Prolog Execution in a Superscalar Prolog System.
J. Inf. Sci. Eng., 1999

1997
Instruction Folding in Java Processor.
Proceedings of the 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 1997

Instruction Cache Prefetching with Extended BTB.
Proceedings of the 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 1997

1996
A Fault-Tolerant Multistage Combining Network.
J. Parallel Distrib. Comput., 1996

Register renaming for x86 superscalar design.
Proceedings of the 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), 1996

1995
An Optimal Instruction Scheduler for Superscalar Processor.
IEEE Trans. Parallel Distrib. Syst., 1995

Memory System Design in Superscalar Processing.
International Journal of High Speed Computing, 1995

An Approximate Agreement Algorithm for Wraparound Meshes.
International Journal of High Speed Computing, 1995

Periodic Adaptive Branch Prediction and its Application in Superscalar Processing in Prolog.
Comput. J., 1995

1994
Effects and Handling of Instruction Class Contention in Superscalar Processing.
International Journal of High Speed Computing, 1994

Optimal multiprocessor task scheduling using dominance and equivalence relations.
Computers & OR, 1994

Branch Prediction for Enhancing Fine-Grained Parallelism in Prolog.
Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994

1993
Reaching Approximate Agreement on Hypercube.
Parallel Computing, 1993

Modeling of Superscalar Instruction Scheduling and Analysis of a Heuristic Scheduling Algorithm.
BIT, 1993

1992
Adoptability and effectiveness of microcode compaction algorithms in superscalar processing.
Parallel Computing, 1992

A bound analysis of scheduling instructions on pipelined processors with a maximal delay of one cycle.
Parallel Computing, 1992

Vectorization of Sorting Algorithms.
International Journal of High Speed Computing, 1992

Upper Bound Analysis of Scheduling Arbitrary-Delay Instructions on Typed Pipelined Processors.
International Journal of High Speed Computing, 1992

1991
An Or-Parallel Inference Model Based on Multi RISC-Style Processing System.
J. Inf. Sci. Eng., 1991

1989
Design of Dual-ALU CRISC and Its Concurrent Execution .
J. Inf. Sci. Eng., 1989


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