Jeng-Jie Peng

According to our database, Jeng-Jie Peng authored at least 6 papers between 1998 and 2003.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2003

Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC.

Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits.

Ming-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002

Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits.

Jeng-Jie Peng, Ming-Dou Ker, Hsin-Chin Jiang

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

ESD test methods on integrated circuits: an overview.

Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's.

Ming-Dou Ker, Hsin-Chin Jiang, Jeng-Jie Peng, Tzay-Luen Shieh

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

1998

Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology.

Ming-Dou Ker, Jeng-Jie Peng

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998