Hamid Sarbazi-Azad
Orcid: 0000-0003-4079-8603Affiliations:
- Sharif University of Technology, Department of Computer Engineering, Tehran, Iran
According to our database1,
Hamid Sarbazi-Azad
authored at least 349 papers
between 1999 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Proc. ACM Meas. Anal. Comput. Syst., 2024
2023
Fast and scalable quantum computing simulation on multi-core and many-core platforms.
Quantum Inf. Process., May, 2023
IEEE Trans. Computers, March, 2023
Proceedings of the International Symposium on Computer Architecture and High Performance Computing Workshops , 2023
Proceedings of the 16th International Workshop on Network on Chip Architectures, 2023
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Venice: Improving Solid-State Drive Parallelism at Low Cost via Conflict-Free Accesses.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
2022
IEEE Trans. Emerg. Top. Comput., 2022
Proc. ACM Meas. Anal. Comput. Syst., 2022
Adv. Comput., 2022
Chapter Three - A power-performance balanced network-on-chip for mixed CPU-GPU systems.
Adv. Comput., 2022
Morpheus: Extending the Last Level Cache Capacity in GPU Systems Using Idle GPU Core Resources.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
ACM Trans. Archit. Code Optim., 2021
Appl. Math. Comput., 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Understanding Power Consumption and Reliability of High-Bandwidth Memory with Voltage Underscaling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
ACM Trans. Parallel Comput., 2020
Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation.
CoRR, 2020
CoRR, 2020
IEEE Comput. Archit. Lett., 2020
Adv. Comput., 2020
Adv. Comput., 2020
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration.
Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2020
2019
ACM Trans. Design Autom. Electr. Syst., 2019
ACM Trans. Comput. Syst., 2019
IEEE Trans. Computers, 2019
ACM Trans. Archit. Code Optim., 2019
Future Gener. Comput. Syst., 2019
ACM Comput. Surv., 2019
IEEE Comput. Archit. Lett., 2019
Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch Boxes.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
2018
ACM Trans. Parallel Comput., 2018
ACM Trans. Design Autom. Electr. Syst., 2018
ACM Trans. Design Autom. Electr. Syst., 2018
Classified Round Robin: A Simple Prioritized Arbitration to Equip Best Effort NoCs With Effective Hard QoS.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Improving MLC PCM Performance through Relaxed Write and Read for Intermediate Resistance Levels.
ACM Trans. Archit. Code Optim., 2018
CoRR, 2018
CoRR, 2018
Parallelizing Bisection Root-Finding: A Case for Accelerating Serial Algorithms in Multicore Substrates.
CoRR, 2018
IEEE Comput. Archit. Lett., 2018
IEEE Comput. Archit. Lett., 2018
Adv. Comput., 2018
Chapter Two - Revisiting Processor Allocation and Application Mapping in Future CMPs in Dark Silicon Era.
Adv. Comput., 2018
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
2017
Efficient Mapping of Applications for Future Chip-Multiprocessors in Dark Silicon Era.
ACM Trans. Design Autom. Electr. Syst., 2017
Endurance-Aware Security Enhancement in Non-Volatile Memories Using Compression and Selective Encryption.
IEEE Trans. Computers, 2017
IEEE Comput. Archit. Lett., 2017
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017
Proceedings of the 2017 International Conference on Networking, Architecture, and Storage, 2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2016
J. Supercomput., 2016
A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I/O Characterization.
IEEE Trans. Computers, 2016
IEEE Trans. Computers, 2016
Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems.
IEEE Trans. Computers, 2016
Microprocess. Microsystems, 2016
Power- and performance-efficient cluster-based network-on-chip with reconfigurable topology.
Microprocess. Microsystems, 2016
Microprocess. Microsystems, 2016
Microprocess. Microsystems, 2016
Comput. Electr. Eng., 2016
TBM: Twin Block Management Policy to Enhance the Utilization of Plane-Level Parallelism in SSDs.
IEEE Comput. Archit. Lett., 2016
Proceedings of the 24th Euromicro International Conference on Parallel, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Quantifying the difference in resource demand among classic and modern NoC workloads.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Efficient processor allocation in a reconfigurable CMP architecture for dark silicon era.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Captopril: Reducing the pressure of bit flips on hot locations in non-volatile main memories.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
ACM Trans. Design Autom. Electr. Syst., 2015
ACM Trans. Design Autom. Electr. Syst., 2015
Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths.
Integr., 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the 2015 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
An efficient DVS scheme for on-chip networks using reconfigurable Virtual Channel allocators.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
J. Supercomput., 2014
J. Supercomput., 2014
Microprocess. Microsystems, 2014
A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure.
Comput. Electr. Eng., 2014
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
A reconfigurable network-on-chip architecture for heterogeneous CMPs in the dark-silicon era.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
A compression-based morphable PCM architecture for improving resistance drift tolerance.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014
2013
Optimum hello interval for a connected homogeneous topology in mobile wireless sensor networks.
Telecommun. Syst., 2013
ACM Trans. Embed. Comput. Syst., 2013
IEEE Trans. Computers, 2013
Math. Comput. Model., 2013
Using task migration to improve non-contiguous processor allocation in NoC-based CMPs.
J. Syst. Archit., 2013
J. Comput. Syst. Sci., 2013
Efficient genetic based topological mapping using analytical models for on-chip networks.
J. Comput. Syst. Sci., 2013
Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip.
Int. J. Adapt. Resilient Auton. Syst., 2013
Network-on-SSD: A Scalable and High-Performance Communication Design Paradigm for SSDs.
IEEE Comput. Archit. Lett., 2013
Power and Performance Efficient Partial Circuits in Packet-Switched Networks-on-Chip.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013
2012
J. Supercomput., 2012
Microprocess. Microsystems, 2012
Microprocess. Microsystems, 2012
J. Netw. Comput. Appl., 2012
Supporting non-contiguous processor allocation in mesh-based chip multiprocessors using virtual point-to-point links.
IET Comput. Digit. Tech., 2012
A Game Theoretical Thermal - Aware Run - Time Task Synchronization Method for Multiprocessor Systems - on - Chip.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Multispanning Tree Zone-Ordered Label-Based Routing Algorithms for Irregular Networks.
IEEE Trans. Parallel Distributed Syst., 2011
J. Parallel Distributed Comput., 2011
J. Parallel Distributed Comput., 2011
Inf. Process. Lett., 2011
On the Topological Properties of Grid-Based Interconnection Networks: Surface Area and Volume of Radial Spheres.
Comput. J., 2011
Modeling the effects of hot-spot traffic load on the performance of wormhole-switched hypermeshes.
Comput. Electr. Eng., 2011
Ad Hoc Networks, 2011
Proceedings of the 19th International Euromicro Conference on Parallel, 2011
Proceedings of the 19th International Euromicro Conference on Parallel, 2011
Proceedings of the 12th International Conference on Parallel and Distributed Computing, 2011
Proceedings of the IEEE 36th Conference on Local Computer Networks, 2011
High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
A reconfigurable fault-tolerant routing algorithm to optimize the network-on-chip performance and latency in presence of intermittent and permanent faults.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point links.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011
2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Power-Performance Analysis of Networks-on-Chip With Arbitrary Buffer Allocation Schemes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
The 2D SEM: A novel high-performance and low-power mesh-based topology for networks-on-chip.
Int. J. Parallel Emergent Distributed Syst., 2010
Performance analysis of opportunistic broadcast for delay-tolerant wireless sensor networks.
J. Syst. Softw., 2010
Corrigendum to "A general methodology for direction-based irregular routing algorithms" [J. Parallel Distrib. Comput. 70 (2010) 363-370]
J. Parallel Distributed Comput., 2010
J. Parallel Distributed Comput., 2010
J. Parallel Distributed Comput., 2010
Comput. Electr. Eng., 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Improving the performance of deadlock recovery based routing in irregular mesh NoCs using added mesh-like links.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 47th Design Automation Conference, 2010
2009
Adaptive routing in wormhole-switched necklace-cubes: Analytical modelling and performance comparison.
Simul. Model. Pract. Theory, 2009
Discret. Math., 2009
Comput. Networks, 2009
Chromatic sets of power graphs and their application to resource placement in multicomputer networks.
Comput. Math. Appl., 2009
Clust. Comput., 2009
Proceedings of the 17th Euromicro International Conference on Parallel, 2009
Performance and power efficient on-chip communication using adaptive virtual point-to-point connections.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the 10th International Symposium on Pervasive Systems, 2009
Routing, data gathering, and neighbor discovery in delay-tolerant wireless sensor networks.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
Proceedings of the 23rd international conference on Supercomputing, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Parallel Lagrange interpolation on <i>k</i> -ary <i>n</i> -cubes with maximum channel utilization.
J. Supercomput., 2008
An accurate mathematical performance model of partially adaptive routing in binary n-cube multiprocessors.
Math. Comput. Model., 2008
Some topological and combinatorial properties of WK-recursive mesh and WK-pyramid interconnection networks.
J. Syst. Archit., 2008
Analytic performance comparison of hypercubes and star graphs with implementation constraints.
J. Comput. Syst. Sci., 2008
Future Gener. Comput. Syst., 2008
Proceedings of the 16th Euromicro International Conference on Parallel, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008
Proceedings of the 9th International Symposium on Parallel Architectures, 2008
Proceedings of the 9th International Symposium on Parallel Architectures, 2008
One-to-one and One-to-many node-disjoint Routing Algorithms for WK-Recursive networks.
Proceedings of the 9th International Symposium on Parallel Architectures, 2008
Mesh Connected Crossbars: A Novel NoC Topology with Scalable Communication Bandwidth.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the Distributed Computing and Networking, 9th International Conference, 2008
Proceedings of the Distributed Computing and Networking, 9th International Conference, 2008
Proceedings of the Computational Science and Its Applications - ICCSA 2008, International Conference, Perugia, Italy, June 30, 2008
The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networks.
Proceedings of the 26th International Conference on Computer Design, 2008
The Effect of Network Topology and Channel Labels on the Performance of Label-Based Routing Algorithms.
Proceedings of the Computational Science, 2008
Proceedings of the Algorithms and Architectures for Parallel Processing, 2008
Proceedings of the Euro-Par 2008, 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Proceedings of the Advances in Computer Science and Engineering, 2008
Proceedings of the Advances in Computer Science and Engineering, 2008
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
Proceedings of the 22nd International Conference on Advanced Information Networking and Applications, 2008
Proceedings of the 22nd International Conference on Advanced Information Networking and Applications, 2008
Proceedings of the 22nd International Conference on Advanced Information Networking and Applications, 2008
Proceedings of the 22nd International Conference on Advanced Information Networking and Applications, 2008
2007
Comparative analytical performance evaluation of adaptivity in wormhole-switched hypercubes.
Simul. Model. Pract. Theory, 2007
An accurate performance model of fully adaptive routing in wormhole-switched two-dimensional mesh multicomputers.
Microprocess. Microsystems, 2007
Mathematical performance modelling of adaptive wormhole routing in optoelectronic hypercubes.
J. Parallel Distributed Comput., 2007
An empirical performance analysis of minimal and non-minimal routing in cube-based OTIS multicomputers.
J. High Speed Networks, 2007
The performance of synchronous parallel polynomial root extraction on a ring multicomputer.
Clust. Comput., 2007
Proceedings of the Eighth International Conference on Parallel and Distributed Computing, 2007
Proceedings of the Eighth International Conference on Parallel and Distributed Computing, 2007
Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007
Proceedings of the Parallel and Distributed Processing and Applications, 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Accelerating 3-D capacitance extraction in deep sub-micron VLSI design using vector/parallel computing.
Proceedings of the 13th International Conference on Parallel and Distributed Systems, 2007
Lifetime analysis of the logical topology constructed by homogeneous topology control in wireless mobile networks.
Proceedings of the 13th International Conference on Parallel and Distributed Systems, 2007
Proceedings of the 13th International Conference on Parallel and Distributed Systems, 2007
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007
Empirical Performance Evaluation of Adaptive Routing in Necklace Hypercubes: A Comparative Study.
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007
Proceedings of the 25th International Conference on Computer Design, 2007
Proceedings of the High Performance Computing and Communications, 2007
Proceedings of the High Performance Computing and Communications, 2007
Proceedings of the Computer Science, 2007
Proceedings of the Computer Science, 2007
XMulator: A Listener-Based Integrated Simulation Platform for Interconnection Networks.
Proceedings of the First Asia International Conference on Modelling and Simulation, 2007
Proceedings of the First Asia International Conference on Modelling and Simulation, 2007
Simulation-Based Performance Evaluation of Deterministic Routing in Necklace Hypercubes.
Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007
Proceedings of the Advances in Computer Systems Architecture, 2007
Proceedings of the Advances in Computer Systems Architecture, 2007
2006
Simul. Model. Pract. Theory, 2006
Performance evaluation of communication networks for parallel and distributed systems.
Parallel Comput., 2006
Int. J. High Perform. Comput. Netw., 2006
Analytical performance modelling of partially adaptive routing in wormhole hypercubes.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Analytical performance modelling of adaptive wormhole routing in the star interconnection network.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
The impacts of timing constraints on virtual channels multiplexing in interconnect networks.
Proceedings of the 25th IEEE International Performance Computing and Communications Conference, 2006
Analytical Performance Comparison of Deterministic, Partially- and Fully-Adaptive Routing Algorithms in Binary n-Cubes.
Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006
A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Proceedings of the Computer Science, 2006
Proceedings of the 1st International ICST Conference on Bio Inspired Models of Network, 2006
Proceedings of the 20th International Conference on Advanced Information Networking and Applications (AINA 2006), 2006
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006
2005
A Performance Model of Software-based Deadlock Recovery Routing Algorithm in Hypercubes.
Parallel Process. Lett., 2005
Performance modeling and evaluation of high-performance parallel and distributed systems.
Perform. Evaluation, 2005
Design and performance of networks for super-, cluster-, and grid-computing: Part II.
J. Parallel Distributed Comput., 2005
J. Parallel Distributed Comput., 2005
Constraint-Based Performance Analysis of k Ary n -Cube Networks
Int. J. Comput. Their Appl., 2005
Design and performance of a pixel-level pipelined-parallel architecture for high speed wavelet-based image compression.
Comput. Electr. Eng., 2005
The necklace-hypercube: a well scalable hypercube-based interconnection network for multiprocessors.
Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), 2005
The recursive transpose-connected cycles (RTCC) interconnection network for multiprocessors.
Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), 2005
Proceedings of the 8th International Symposium on Parallel Architectures, 2005
Proceedings of the 8th International Symposium on Parallel Architectures, 2005
Proceedings of the 8th International Symposium on Parallel Architectures, 2005
Proceedings of the 8th International Symposium on Parallel Architectures, 2005
Proceedings of the Parallel and Distributed Processing and Applications, 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
The Effect of Virtual Channel Organization on the Performance of Interconnection Networks.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
An Empirical Comparison of OTIS-Mesh and OTIS-Hypercube Multicomputer Systems under Deterministic Routing.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the 34th International Conference on Parallel Processing Workshops (ICPP 2005 Workshops), 2005
Performance Evaluation of Fully Adaptive Routing Under Different Workloads and Constant Node Buffer Size.
Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005
Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005
Proceedings of the Distributed and Parallel Computing, 2005
Proceedings of the High Performance Computing and Communications, 2005
A Constraint-Based Performance Comparison of Hypercube and Star Multicomputers with Failures.
Proceedings of the 19th International Conference on Advanced Information Networking and Applications (AINA 2005), 2005
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005
2004
J. Syst. Softw., 2004
Algorithmic Construction of Hamiltonian Cycles in k-Ary n-Cubes.
Int. J. Comput. Their Appl., 2004
Concurr. Pract. Exp., 2004
Constraint-based performance comparison of multi-dimensional interconnection networks with deterministic and adaptive routing strategies.
Comput. Electr. Eng., 2004
The Effect of Adaptivity on the Performance of the OTIS-Hypercube Under Different Traffic Patterns.
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2004
Performance Modeling of Fully Adaptive Wormhole Routing in 2-D Mesh-Connected Multiprocessors.
Proceedings of the 12th International Workshop on Modeling, 2004
Proceedings of the 7th International Symposium on Parallel Architectures, 2004
Proceedings of the Parallel and Distributed Processing and Applications, 2004
Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
An Accurate Combinatorial Model for Performance Prediction of Deterministic Wormhole Routing in Torus Multicomputer Systems.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 18th International Conference on Advanced Information Networking and Applications (AINA 2004), 2004
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004
2003
Analytical modelling of wormhole-routed k-ary n-cubes in the presence of matrix-transpose traffic.
J. Parallel Distributed Comput., 2003
Future Gener. Comput. Syst., 2003
Future Gener. Comput. Syst., 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
2002
A Performance Model of Adaptive Wormhole Routing in <i>k</i>-Ary <i>n</i>-Cubes in the Presence of Digit-Reversal Traffic.
J. Supercomput., 2002
J. Parallel Distributed Comput., 2002
Performance Analysis of Deterministic Routing in Workhole <i>k</i>-Ary <i>n</i>-Cubes with Virtual Channels.
J. Interconnect. Networks, 2002
Proceedings of the 2002 ACM Symposium on Applied Computing (SAC), 2002
Comparative Analysis of Adaptive Wormhole Routing in Tori and Hypercubes in the Presence of Hotspot Traffic.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
2001
PhD thesis, 2001
An Analytical Model of Adaptive Wormhole Routing in Hypercubes in the Presence of Hot Spot Traffic.
IEEE Trans. Parallel Distributed Syst., 2001
Analytical Modeling of Wormhole-Routed k-Ary n-Cubes in the Presence of Hot-Spot Traffic.
IEEE Trans. Computers, 2001
An accurate analytical model of adaptive wormhole routing in k-ary n-cubes interconnection networks.
Perform. Evaluation, 2001
Parallel Comput., 2001
Parallel Algorithms Appl., 2001
On the performance of adaptive wormhole routing in the bi-directional torus network: a hot spot analysis.
Microprocess. Microsystems, 2001
Proceedings of the 9th International Workshop on Modeling, 2001
Proceedings of the Eigth International Conference on Parallel and Distributed Systems, 2001
Analysis of Deterministic Routing in <i>k</i>-Ary <i>n</i>-Cubes with Virtual Channels.
Proceedings of the Eigth International Conference on Parallel and Distributed Systems, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
2000
Microprocess. Microsystems, 2000
Int. J. High Speed Comput., 2000
Comput. J., 2000
Proceedings of the MASCOTS 2000, Proceedings of the 8th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 29 August, 2000
An Analytic Model for Communication Latency in Wormhole-Switched <i>k</i>-ary <i>n</i>-Cube Interconnection Networks with Digit-Reversal Traffic.
Proceedings of the High Performance Computing, Third International Symposium, 2000
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000
An Analytical Model of Fully-Adaptive Wormhole-Routed k-Ary n-Cubes in the Presence of Hot Spot Traffic.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000
A Performance Model of Adaptive Routing in k-Ary n-Cubes with Matrix-Transpose Traffic.
Proceedings of the 2000 International Conference on Parallel Processing, 2000
Proceedings of the Seventh International Conference on Parallel and Distributed Systems, 2000
1999
Proceedings of the Parallel Computation, 1999