Arash Tavakkol

Orcid: 0000-0003-3859-1259

According to our database1, Arash Tavakkol authored at least 26 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Venice: Improving Solid-State Drive Parallelism at Low Cost via Conflict-Free Accesses.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2022
Quick Generation of SSD Performance Models Using Machine Learning.
IEEE Trans. Emerg. Top. Comput., 2022

2021
PLMC: A Predictable Tail Latency Mode Coordinator for Shared NVMe SSD with Multiple Hosts.
Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2021

2019
ITAP: Idle-Time-Aware Power Management for GPU Execution Units.
ACM Trans. Archit. Code Optim., 2019

Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices.
CoRR, 2019

2018
Enabling Efficient RDMA-based Synchronous Mirroring of Persistent Memory Transactions.
CoRR, 2018

Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices.
Proceedings of the 16th USENIX Conference on File and Storage Technologies, 2018

2016
Performance Evaluation of Dynamic Page Allocation Strategies in SSDs.
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2016

TBM: Twin Block Management Policy to Enhance the Utilization of Plane-Level Parallelism in SSDs.
IEEE Comput. Archit. Lett., 2016

2014
Unleashing the potentials of dynamism for page allocation strategies in SSDs.
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

Design for scalability in enterprise SSDs.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
Network-on-SSD: A Scalable and High-Performance Communication Design Paradigm for SSDs.
IEEE Comput. Archit. Lett., 2013

2011
Application-Aware Topology Reconfiguration for On-Chip Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point links.
Proceedings of the Design, Automation and Test in Europe, 2011

Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths.
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011

2010
Virtual Point-to-Point Connections for NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

An efficient dynamically reconfigurable on-chip network architecture.
Proceedings of the 47th Design Automation Conference, 2010

2009
Performance and power efficient on-chip communication using adaptive virtual point-to-point connections.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

2008
Virtual Point-to-Point Links in Packet-Switched NoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Energy analysis of re-injection based deadlock recovery routing algorithms.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Mesh Connected Crossbars: A Novel NoC Topology with Scalable Communication Bandwidth.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

Mathematical analysis of buffer sizing for Network-on-Chips under multimedia traffic.
Proceedings of the 26th International Conference on Computer Design, 2008

The Effect of Network Topology and Channel Labels on the Performance of Label-Based Routing Algorithms.
Proceedings of the Computational Science, 2008

An Adaptive Software-Based Deadlock Recovery Technique.
Proceedings of the 22nd International Conference on Advanced Information Networking and Applications, 2008


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