Jeonghyu Yang

Orcid: 0009-0001-1364-4505

According to our database1, Jeonghyu Yang authored at least 9 papers between 2022 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2025
A Driver-Current-Regulated 120-Gb/s PAM-8 7-bit DAC-Based Transmitter in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2025

A 96-Gb/s 1.6-V<sub>ppd</sub> PAM-8 Transmitter With High-Swing and Low-Loading Cascaded Driver in 40-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., July, 2025

100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology.
IEEE J. Solid State Circuits, February, 2025

A 96-Gb/s PAM-8 Transmitter with Transition-Boosted Current-Mode Logic Driver in 40-nm CMOS for Wireline Communication.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A 56-Gb/s 0.39-pJ/bit PAM-4 Transmitter Frontend with Shunt-Ffe Tail-Less Driver and External Bias-Tees.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

2023
A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
A 32-Gb/s High-Swing PAM-4 Current-Mode Driver with Current-Bleeding Cascode Technique and Capacitive-Coupled Pre-drivers in 40-nm CMOS for Short-Reach Wireline Communications.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022


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