Jaeduk Han
Orcid: 0000-0001-8798-1275
According to our database1,
Jaeduk Han
authored at least 55 papers
between 2011 and 2024.
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Bibliography
2024
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
A 35-Gb/s PAM-4 Transmitter With 7B4Q Full-Transition Avoidance and Area-Efficient Gm-Boosting Techniques.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
2023
LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023
A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies.
IEEE Access, 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
2022
A 1.5-GS/s 6-bit Single-Channel Loop-Unrolled SAR ADC With Speculative CDAC Switching Control Technique in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
CoRR, 2022
A Discharge-Path-Based Sensing Circuit With OTS Snapback Current Protection for Phase Change Memories.
IEEE Access, 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 32-Gb/s High-Swing PAM-4 Current-Mode Driver with Current-Bleeding Cascode Technique and Capacitive-Coupled Pre-drivers in 40-nm CMOS for Short-Reach Wireline Communications.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
2021
LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Automatic prior selection for image deconvolution: Statistical modeling on natural images.
Signal Process., 2021
8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology.
Proceedings of the 18th International SoC Design Conference, 2021
Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM Technologies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE Trans. Circuits Syst. Video Technol., 2020
Multi-Frame Depth Super-Resolution for ToF Sensor With Total Variation Regularized L1 Function.
IEEE Access, 2020
Design Techniques for Robust and Area-efficient Current Sources in Nanometer CMOS Technology.
Proceedings of the International SoC Design Conference, 2020
Proceedings of the Image Processing: Algorithms and Systems XVIII, 2020
2019
A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
Multi-frame super-resolution utilizing spatially adaptive regularization for ToF camera.
Proceedings of the Image Processing: Algorithms and Systems XVII, 2019
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
Permuted Coordinate-Wise Optimizations Applied to Lp-Regularized Image Deconvolution.
IEEE Trans. Image Process., 2018
A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards.
IEEE Trans. Ind. Electron., 2018
An Automated SerDes Frontend Generator Verified with a 16NM Instance Achieving 15 GB/S at 1.96 PJ/Bit.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET.
IEEE J. Solid State Circuits, 2017
Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology.
IEEE J. Solid State Circuits, 2017
6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the Image Processing: Algorithms and Systems XV, Burlingame, CA, USA, 29 January 2018, 2017
A 0.37mm<sup>2</sup> LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2<sup>n</sup>3<sup>m</sup>5<sup>k</sup> FFT accelerator integrated with a RISC-V core in 16nm FinFET.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology.
IEEE J. Solid State Circuits, 2016
2015
Proceedings of the Symposium on VLSI Circuits, 2015
2011
A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011