Jesse Cirimelli-Low

According to our database, Jesse Cirimelli-Low authored at least 4 papers between 2019 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Heterogeneous Memory Design Exploration for AI Accelerators with a Gain Cell Memory Compiler.

Xinxin Wang, Lixian Yan, Shuhan Liu, Luke Upton, Zhuoqi Cai, Yiming Tan, Shengman Li, Koustav Jana, Peijing Li, Jesse Cirimelli-Low, Thierry Tambe, Matthew Guthaus, H.-S. Philip Wong

CoRR, February, 2026

2025

OpenGCRAM: An Open-Source Gain Cell Compiler Enabling Design-Space Exploration for AI Workloads.

Xinxin Wang, Lixian Yan, Shuhan Liu, Luke Upton, Zhuoqi Cai, Yiming Tan, Shengman Li, Koustav Jana, Peijing Li, Jesse Cirimelli-Low, Thierry Tambe, Matthew Guthaus, H.-S. Philip Wong

CoRR, July, 2025

2023

SRAM Design with OpenRAM in SkyWater 130nm.

Jesse Cirimelli-Low, Muhammad Hadir Khan, Samuel Crow, Amogh Lonkar, Bugra Onal, Andrew D. Zonenberg, Matthew R. Guthaus

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2019

Automated Synthesis of Multi-Port Memories and Control.

Hunter Nichols, Michael Grimes, Jennifer Sowash, Jesse Cirimelli-Low, Matthew R. Guthaus

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019