Ji-Yong Jeong

Orcid: 0000-0003-1056-921X

According to our database1, Ji-Yong Jeong authored at least 10 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
A Source-Driver IC Including Power-Switching Fast-Slew-Rate Buffer and 8Gb/s Effective 3-Tap DFE Receiver Achieving 4.9mV DVRMS and 17V/ps Slew Rate for 8K Displays and Beyond.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2021
A High-Speed and Energy-Efficient Multi-Bit Cyclic ADC Using Single-Slope Quantizer for CMOS Image Sensors.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A High Frame Rate Analog Front-End IC With Piezoelectric Micromachined Ultrasound Transducers Using Analog Multi-Line Acquisition for Ultrasound Imaging Systems.
IEEE Access, 2021

2018
A Low-Power Analog Delay Line Using a Current-Splitting Method for 3-D Ultrasound Imaging Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 3.9-kHz Frame Rate and 61.0-dB SNR Analog Front-End IC With 6-bit Pressure and Tilt Angle Expressions of Active Stylus Using Multiple-Frequency Driving Method for Capacitive Touch Screen Panels.
IEEE J. Solid State Circuits, 2018

Multi-way interactive capacitive touch system with palm rejection of active stylus for 86" touch screen panels.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
9.6 A 3.9kHz-frame-rate capacitive touch system with pressure/tilt angle expressions of active stylus using multiple-frequency driving method for 65″ 104×64 touch screen panel.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2007
The Wide Input Range Automatic-Threshold Control Circuit for High Definition Digital Audio Interface.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
New Battery Status Checking Method for Implantable Biomedical Applications.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006


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