Keiji Tatani

Orcid: 0000-0003-1685-2200

According to our database1, Keiji Tatani authored at least 6 papers between 2018 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
7.5 a 26.0mW 30fps 400X300-Pixel SWIR Ge-SPAD dToF Range Sensor with Programmable Macro-Pixels and Integrated Histogram Processing for Low-Power AR/VR Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2022
A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide-Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2019
A 6.9 μm Pixel-Pitch 3D Stacked Global Shutter CMOS Image Sensor with 3M Cu-Cu connections.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018
A Stacked CMOS Image Sensor With Array-Parallel ADC Architecture.
IEEE J. Solid State Circuits, 2018

A 6.9-µm Pixel-Pitch Back-Illuminated Global Shutter CMOS Image Sensor With Pixel-Parallel 14-Bit Subthreshold ADC.
IEEE J. Solid State Circuits, 2018



  Loading...