Jia Park

According to our database, Jia Park authored at least 4 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A 4 × 32 Gb/s 1.8 pJ/bit Collaborative Baud-Rate CDR With Background Eye-Climbing Algorithm and Low-Power Global Clock Distribution.

Jihee Kim, Jia Park, Jiwon Shin, Hanseok Kim, Kahyun Kim, Haengbeom Shin, Ha-Jung Park, Woo-Seok Choi

IEEE J. Solid State Circuits, August, 2025

22.1 A 0.275pJ/b 42Gb/s/pin Clock-Referenced PAM3 Transceiver Tolerant to Supply Noise, Reference Offset and Crosstalk for Chiplets and Short-Reach Memory Interfaces.

Kahyun Kim, Jung-Hun Park, Ha-Jung Park, Jia Park, Jihee Kim, Woo-Seok Choi

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2023

An Analog Integrate-and-Fire Neuron with Robust Soft Reset Mechanism.

Jia Park, Woo-Seok Choi

Proceedings of the 20th International SoC Design Conference, 2023

2022

Impact of Oscillator Phase Noise on Time-Domain SNN Performance.

Jia Park, Woo-Seok Choi

Proceedings of the 19th International SoC Design Conference, 2022