Hanseok Kim

Orcid: 0009-0008-2365-4230

According to our database1, Hanseok Kim authored at least 13 papers between 2011 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A 42-Gb/s Noise-Tolerant Single-Ended Clock-Referenced PAM3 Transceiver for Chiplet Interfaces.
IEEE J. Solid State Circuits, January, 2026

2025
A 0.65-pJ/bit 3.6-TB/s/mm I/O Interface With XTalk Minimizing Affine Signaling for Next-Generation HBM With High Interconnect Density.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025

A 4 × 32 Gb/s 1.8 pJ/bit Collaborative Baud-Rate CDR With Background Eye-Climbing Algorithm and Low-Power Global Clock Distribution.
IEEE J. Solid State Circuits, August, 2025

Implementing FFE-MLSD With Improved BER and Reduced Complexity for Long-Reach PAM4 Wireline Receivers.
IEEE Access, 2025

2024
A comprehensive comparison study of ML models for multistage APT detection: focus on data preprocessing and resampling.
J. Supercomput., July, 2024

2022
A 0.6 ㎛ Small Pixel for High Resolution CMOS Image Sensor with Full Well Capacity of 10, 000e- by Dual Vertical Transfer Gate Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Improving Spiking Neural Network Accuracy Using Time-based Neurons.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Energy-Efficient High-Accuracy Spiking Neural Network Inference Using Time-Domain Neurons.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2013
A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm.
IEEE J. Solid State Circuits, 2013

2012
Direction-based topology control algorithm for mobile ad-hop networks.
Proceedings of the International Symposium on Communications and Information Technologies, 2012

A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A 5-Gbps 1.7 pJ/bit ditherless CDR with optimal phase interval detection.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Fast and accurate event-driven simulation of mixed-signal systems with data supplementation.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011


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