Woo-Seok Choi
Orcid: 0000-0002-3556-8689
According to our database1,
Woo-Seok Choi
authored at least 56 papers
between 2008 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023
A Context-Aware Readout System for Sparse Touch Sensing Array Using Ultra-Low-Power Always-On Event Detection.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023
Verification and performance comparison of CNN-based algorithms for two-step helmet-wearing detection.
Expert Syst. Appl., September, 2023
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
Sensors, February, 2023
CoRR, 2023
A Pixel Driver Design Technique to Obtain a High-Quality Depth Map in Indirect Time-of-Flight Sensors.
Proceedings of the 20th International SoC Design Conference, 2023
Design of Energy-Efficient Cryptographically Secure Pseudo-Random Number Generators Using High-Level Synthesis.
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Near-Threshold Ring-Oscillator-Based ILCM with Edge-Selective Error Detector Achieving -64 dBc Reference-Spur and -239 dB FoM.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation.
IEEE J. Solid State Circuits, 2022
A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns.
IEEE J. Solid State Circuits, 2022
0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Performance Variability Modeling of Analog Circuits Using Improved Orthogonal Matching Pursuit.
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Energy-Efficient High-Accuracy Spiking Neural Network Inference Using Time-Domain Neurons.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
IEEE J. Solid State Circuits, 2020
2019
A 0.016 mm<sup>2</sup> 0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS.
IEEE J. Solid State Circuits, 2019
2018
A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes.
IEEE J. Solid State Circuits, 2018
A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation.
IEEE J. Solid State Circuits, 2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition.
IEEE J. Solid State Circuits, 2016
23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method.
IEEE J. Solid State Circuits, 2015
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC.
IEEE J. Solid State Circuits, 2015
A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links.
IEEE J. Solid State Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop.
IEEE J. Solid State Circuits, 2014
Proceedings of the Symposium on VLSI Circuits, 2014
A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement.
Proceedings of the Symposium on VLSI Circuits, 2014
A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC.
Proceedings of the Symposium on VLSI Circuits, 2014
8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2011
250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS.
IEEE J. Solid State Circuits, 2011
2008
Proceedings of 8th IEEE International Conference on Computer and Information Technology, 2008