Jian Zhang
Orcid: 0000-0003-3822-2533Affiliations:
- Tsinghua University, School of Integrated Circuits, Beijing, China
According to our database1,
Jian Zhang
authored at least 14 papers
between 2021 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
A Broadband Bidirectional Four-Element Four-Beam Beamformer With Compact Floorplan in a 65nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2025
2024
Automatic Design for W-Band Front-End System via Bottom-Up Sizing and Layout Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024
32.8 A 27.8-to-38.7GHz Load-Modulated Balanced Power Amplifier with Scalable 7-to-1 Load-Modulated Power-Combine Network Achieving 27.2dBm Output Power and 28.8%/23.2%/16.3%/11.9% Peak/6/9/12dB Back-Off Efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Fast Surrogate-Assisted Constrained Multiobjective Optimization for Analog Circuit Sizing via Self-Adaptive Incremental Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023
A Hybrid Integrated W-Band 4-Element Phased-Array Transceiver Front-End Achieving 21.6% Full TX Peak PAE at 14.8dBm Output Power and <1°/dB Phase/Gain Resolution in 65-nm CMOS Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A Ka-Band Mutual Coupling Resilient Balanced PA with Magnetic Coupling Self-Cancelling Inductor Achieving 21.2dBm OP1dBand 27.6% PAE1dB.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
Asynchronous Parallel Expected Improvement Matrix-Based Constrained Multi-Objective Optimization for Analog Circuit Sizing.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
An Ultra-compact Bidirectional T/R Folded 25.8-39.2GHz Phased-Array Transceiver Front-End with Embedded TX Power Detection/Self-calibration Path Supporting 64-/256-/512-QAM at 28-/39-GHz band for 5G in 65nm CMOS Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 1V 32.1 dBm 92-to-102GHz Power Amplifier with a Scalable 128-to-1 Power Combiner Achieving 15% Peak PAE in a 65nm Bulk CMOS Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Building Post-layout Performance Model of Analog/RF Circuits by Fine-tuning Technique.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
An Efficient Kriging-based Constrained Multi-objective Evolutionary Algorithm for Analog Circuit Synthesis via Self-adaptive Incremental Learning.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
Proceedings of the International Conference on IC Design and Technology, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021