Jiandong Zang

According to our database, Jiandong Zang authored at least 4 papers between 2020 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A 2× Time-Interleaved 4-GS/s 14-Bit DAC With On-Chip Calibration of Interleaving Nonlinearities.

Zhou Shu, Jiandong Zang, Qinghao Liu, Tantan Zhang, Yuan Gao, Chun-Huat Heng, Yongxin Guo, Zhangming Zhu

IEEE J. Solid State Circuits, November, 2025

2024

An 8 GHz Semi-Digital DLL for CDR in High Speed SerDes Receivers.

Yi Ding, Jiandong Zang, Jun Liu

Proceedings of the 2024 5th International Conference on Computing, 2024

2021

A Low-Area and Low-Power Comma Detection and Word Alignment Circuits for JESD204B/C Controller.

Peng Yin, Zhou Shu, Yingjun Xia, Tianmei Shen, Xiao Guan, Xiaoqin Wang, Umar Mohammad, Jiandong Zang, Dongbing Fu, Xiaoping Zeng, Fang Tang, Amine Bermak

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

A 5-13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process.

Zhou Shu, Shalin Huang, Zhipeng Li, Peng Yin, Jiandong Zang, Dongbing Fu, Fang Tang, Amine Bermak

IEEE Trans. Circuits Syst., 2020