Zhangming Zhu

According to our database1, Zhangming Zhu authored at least 181 papers between 2005 and 2021.

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Bibliography

2021
A Sub-200nW All-in-One Bandgap Voltage and Current Reference Without Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 2.6 GΩ, 1.4 μV<sub>rms</sub> current-reuse instrumentation amplifier for wearable electrocardiogram monitoring.
Microelectron. J., 2021

2020
Ultrawideband Power-Switchable Transmitter With 17.7-dBm Output Power for See-Through-Wall Radar.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A 66-dB Linear Dynamic Range, 100-dB· $\Omega$ Transimpedance Gain TIA With High-Speed PDSH for LiDAR.
IEEE Trans. Instrum. Meas., 2020

An 8-ch LIDAR Receiver Based on TDC With Multi-Interval Detection and Real-Time $In~Situ$ Calibration.
IEEE Trans. Instrum. Meas., 2020

A Dual-Supply Two-Stage CMOS Op-amp for High-Speed Pipeline ADCs Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A CMOS Peak Detect and Hold Circuit With Auto-Adjust Charging Current for NS-Scale Pulse ToF Lidar Application.
IEEE Trans. Circuits Syst., 2020

High Input Impedance Low-Noise CMOS Analog Frontend IC for Wearable Electrocardiogram Monitoring.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 2nd-Order Noise-Shaping SAR ADC With Lossless Dynamic Amplifier Assisted Integrator.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 0.6-V 9-bit 1-MS/s Charging Sharing SAR ADC With Judging-Window Switching Logic and Independent Reset Comparator for Power-Effective Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Low Walk Error Analog Front-End Circuit With Intensity Compensation for Direct ToF LiDAR.
IEEE Trans. Circuits Syst., 2020

A 60-m Range 6.16-mW Laser-Power Linear-Mode LiDAR System With Multiplex ADC/TDC in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Robust Bio-IA With Digitally Controlled DC-Servo Loop and Improved Pseudo-Resistor.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A P&O MPPT With a Novel Analog Power-Detector for WSNs Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS.
IEEE Trans. Circuits Syst., 2020

A 10-bit SAR ADC using novel LSB-first successive approximation for reduced bitcycles.
Microelectron. J., 2020

A 7b 400 ​MS/s pipelined SAR ADC in 65 ​nm CMOS.
Microelectron. J., 2020

Physics based scalable inductance model for three-dimensional solenoid inductors.
Microelectron. J., 2020

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique.
IEEE J. Solid State Circuits, 2020

A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration.
IEEE J. Solid State Circuits, 2020

An Efficient Interface Circuit for Miniature Piezoelectric Energy Harvesting with P-SSHC.
J. Circuits Syst. Comput., 2020

Millimeter-Wave Antenna-in-Package Applications Based on D263T Glass Substrate.
IEEE Access, 2020

A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A 10-Bit 5 MS/s VCO-SAR ADC in 0.18-µm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 1.2-V 2.41-GHz Three-Stage CMOS OTA With Efficient Frequency Compensation Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 0.6-V pseudo-differential OTA with switched-opamp technique for low power applications.
Microelectron. J., 2019

Electromagnetic modeling and analysis of the tapered differential through glass vias.
Microelectron. J., 2019

Broadband inductance modeling of TXVs for 3D interconnection.
Microelectron. J., 2019

A high linear voltage-to-time converter (VTC) with 1.2 V input range for time-domain analog-to-digital converters.
Microelectron. J., 2019

A low cross-regulation and high-efficiency SIDO boost converter with near-threshold start-up.
Microelectron. J., 2019

An encapsulated packet-selection routing for network on chip.
Microelectron. J., 2019

A 15ps resolution time-to-digital converter with on-chip PLL counting for LiDAR multi-object sensors.
Microelectron. J., 2019

A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting.
IEEE J. Solid State Circuits, 2019

A Two-Step ADC With a Continuous-Time SAR-Based First Stage.
IEEE J. Solid State Circuits, 2019

A Low Complexity Digital Foreground Calibration Technique for CMOS Pipelined ADCs.
J. Circuits Syst. Comput., 2019

A Low Power and Low Current-Mismatch Charge Pump with Dynamic Current Compensation.
J. Circuits Syst. Comput., 2019

A Self-Powered P-SSHI Interface Circuit with Adaptive On-Resistance Active Diode for PEH.
J. Circuits Syst. Comput., 2019

A High Gain, 808MHz GBW Four-Stage OTA in 65nm CMOS.
J. Circuits Syst. Comput., 2019

A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A Linear Dynamic Range Receiver With Timing Discrimination for Pulsed TOF Imaging LADAR Application.
IEEE Trans. Instrum. Meas., 2018

Low-Power Single-Ended SAR ADC Using Symmetrical DAC Switching for Image Sensors With Passive CDS and PGA Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Reconfigurable 10-to-12-b 80-to-20-MS/s Bandwidth Scalable SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 77-dB Dynamic Range Low-Power Variable-Gain Transimpedance Amplifier for Linear LADAR.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 0.55-V, 28-ppm/°C, 83-nW CMOS Sub-BGR With UltraLow Power Curvature Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A charge-sharing switching scheme for SAR ADCs in biomedical applications.
Microelectron. J., 2018

A 10-bit 100-MS/s 5.23-mW SAR ADC in 0.18-μm CMOS.
Microelectron. J., 2018

A 1.2 V, 3.0 ppm/°C, 3.6 μA CMOS bandgap reference with novel 3-order curvature compensation.
Microelectron. J., 2018

A dual mode step-down switched-capacitor DC-DC converter with adaptive switch width modulation.
Microelectron. J., 2018

A 10bit 20 kS/s 17.7 nW 9.1ENOB reference-insensitive SAR ADC in 0.18 μm CMOS.
Microelectron. J., 2018

A transconductance-enhancement cascode Miller compensation for low-power multistage amplifiers.
Microelectron. J., 2018

A High Energy Efficiency and Low Common-Mode Voltage Variation Switching Scheme for SAR ADCs.
J. Circuits Syst. Comput., 2018

A Power-Enhanced Active Rectifier with Offset-Controlled Comparator for Self-Powered PEH Systems.
J. Circuits Syst. Comput., 2018

Adaptive On-Time-Controlled PFM Boost Converter with a Below-Threshold Startup Voltage.
J. Circuits Syst. Comput., 2018

A 42ppm/∘C 0.7V 47nW Low-Complexity All-MOSFET Sub-Threshold Voltage Reference.
J. Circuits Syst. Comput., 2018

Analysis and Modeling of a SAR-VCO Hybrid ADC Architecture.
J. Circuits Syst. Comput., 2018

An Energy-Efficient Switching Scheme for Low-Power SAR ADC Design.
J. Circuits Syst. Comput., 2018

Energy-Efficient and Area-Saving Asymmetric Capacitor Switching Scheme for SAR ADCs.
J. Circuits Syst. Comput., 2018

Temperature-dependent characterizations on parasitic capacitance of tapered through silicon via (T-TSV).
IEICE Electron. Express, 2018

A 0.5-nW 29ppm/°C Voltage Reference Circuit.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Inductance of Different Profiles of Through Glass Vias based on magnetic flux density.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

A Background Timing Skew Calibration Technique in Time-Interleaved ADCs With Second Order Compensation.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

A 10-KS/s 625-Hz-Bandwidth 60-dB SNDR Noise-Shaping ADC for Bio-potential Signals Detection Application.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
A 30-W 90% Efficiency Dual-Mode Controlled DC-DC Controller With Power Over Ethernet Interface for Power Device.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Versatile OCP Control Scheme for Discontinuous Conduction Mode Flyback AC/DC Converters.
IEEE Trans. Ind. Electron., 2017

A Compact High-Performance Programmable-Gain Analog Front End for HomePlug AV2 Communication in 0.18- $\mu \text{m}$ CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 58-ppm/°C 40-nW BGR at Supply From 0.5 V for Energy Harvesting IoT Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A dynamic task mapping algorithm for SDNoC.
Microelectron. J., 2017

Design of linear dynamic range and high sensitivity matrix quadrant APDs ROIC for position sensitive detector application.
Microelectron. J., 2017

An active dry electrode ecg interface circuit for wearable sensors.
Microelectron. J., 2017

A low-noise programmable gain amplifier with fully balanced differential difference amplifier and class-AB output stage.
Microelectron. J., 2017

A fair arbitration for Network-on-Chip routing with odd-even turn model.
Microelectron. J., 2017

A current-reuse dual-channel bio-signal amplifier for WBAN nodes.
Microelectron. J., 2017

A high accuracy CMOS subthreshold voltage reference with offset cancellation and thermal compensation.
Microelectron. J., 2017

A 12-bit 200MS/s pipeline ADC with 91 mW power and 66 dB SNDR.
Microelectron. J., 2017

A 0.6 V 31 nW 25 ppm/°C MOSFET-only sub-threshold voltage reference.
Microelectron. J., 2017

A 0.3 V 8-bit 8.9 fJ/con.-step SAR ADC with sub-DAC merged switching for bio-sensors.
Microelectron. J., 2017

Analysis and optimal distribution scheme for SAR-VCO ADCs.
Microelectron. J., 2017

A 0.5-V 9.3-ENOB 68-nW 10-kS/s SAR ADC in 0.18-μm CMOS for biomedical applications.
Microelectron. J., 2017

A Fault-Tolerant Deflection Routing for Network-on-Chip.
J. Circuits Syst. Comput., 2017

A Near-Threshold Voltage Startup Monolithic Boost Converter with Adaptive Sleeping Time Control.
J. Circuits Syst. Comput., 2017

A Novel Interface Circuit with 99.2% MPPT Accuracy and 1.3% THD for Energy Harvesting.
J. Circuits Syst. Comput., 2017

An efficient energy and thermal-aware mapping for regular network-on-chip.
IEICE Electron. Express, 2017

CDS Circuit with High-Performance VGA Functionality and Its Design Procedure.
Circuits Syst. Signal Process., 2017

A Fast-Settling Three-Stage Amplifier Using Regular Miller Plus Reversed Indirect Compensation.
Circuits Syst. Signal Process., 2017

2016
A 0.45 V, Nano-Watt 0.033% Line Sensitivity MOSFET-Only Sub-Threshold Voltage Reference With no Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 0.5-V 1.3-µW Analog Front-End CMOS Circuit.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A low-distortion CMOS analogue voltage follower for high-speed ADCs.
Microelectron. J., 2016

Analysis and optimization of the two-stage pipelined SAR ADCs.
Microelectron. J., 2016

A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18 µm CMOS.
Microelectron. J., 2016

Analysis of propagation delay and repeater insertion in single-walled carbon nanotube bundle interconnects.
Microelectron. J., 2016

An automatic mode low-jitter pulsewidth control loop with broadband operation frequency.
Microelectron. J., 2016

A background fast convergence algorithm for timing skew in time-interleaved ADCs.
Microelectron. J., 2016

An asynchronous 12-bit 50 MS/s rail-to-rail Pipeline-SAR ADC in 0.18 μm CMOS.
Microelectron. J., 2016

A 0.5-V power-efficient low-noise CMOS instrumentation amplifier for wireless biosensor.
Microelectron. J., 2016

A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS.
J. Circuits Syst. Comput., 2016

A High Efficiency Self-Powered Rectifier for Piezoelectric Energy Harvesting Systems.
J. Circuits Syst. Comput., 2016

A Dual Band RF Energy Harvester with Hybrid Threshold Voltage Self-Compensation.
J. Circuits Syst. Comput., 2016

Synthesis of resonators filters with arbitrary mixed topology using hybrid method.
IEICE Electron. Express, 2016

An Improved-Linearity, Single-Stage Variable-Gain Amplifier Using Current Squarer for Wider Gain Range.
Circuits Syst. Signal Process., 2016

An Ultra-Low-Power Integrated RF Energy Harvesting System in 65-nm CMOS Process.
Circuits Syst. Signal Process., 2016

A 0.5 V, 40nW voltage reference for WBAN devices.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

A 0.8-V 1.7-μW25.9-fJ continuous-time sigma-delta modulator for biomedical applications.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
A High-SFDR 14-bit 500 MS/s Current-Steering D/A Converter in 0.18~µm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 µm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18- μm CMOS for Medical Implant Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Floating Buck Controlled Multi-Mode Dimmable LED Driver Using a Stacked NMOS Switch.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 0.45-V, 14.6-nW CMOS Subthreshold Voltage Reference With No Resistors and No BJTs.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A low-jitter wide-range duty cycle corrector for high-speed high-precision ADC.
Microelectron. J., 2015

A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS.
Microelectron. J., 2015

Calibration algorithm for 16-bit voltage-mode R-2R DAC.
Microelectron. J., 2015

A 5-GHz LC VCO with digital AAC and AFBS for 2.4 GHz ZigBee transceiver applications.
Microelectron. J., 2015

A background digital calibration of split-capacitor 16-bit SAR ADC with sub-binary architecture.
Microelectron. J., 2015

A Routing Aggregation for Load Balancing Network-on-Chip.
J. Circuits Syst. Comput., 2015

A Low Standby Power Primary-Side Regulated Flyback Controller with Fast Dynamic Response.
J. Circuits Syst. Comput., 2015

Analog-Based CMOS Duty Cycle Corrector with 50-800 MHz Operating Range.
J. Circuits Syst. Comput., 2015

A Gain-Tunable Output Buffer for Audio-DAC with Common-Mode Output Independent of Gain Variation.
J. Circuits Syst. Comput., 2015

An 8-Bit 0.333-2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS.
J. Circuits Syst. Comput., 2015

Feed-Forward Slope Compensated PFC for Chaos Control.
J. Circuits Syst. Comput., 2015

A High Linear CMOS Body Effect Compensation Bootstrapped Switch.
J. Circuits Syst. Comput., 2015

Variable resolution SAR ADC architecture with 99.6% reduction in switching energy over conventional scheme.
IEICE Electron. Express, 2015

Energy-efficient and reference-free monotonic capacitor switching scheme with fewest switches for SAR ADC.
IEICE Electron. Express, 2015

Energy-efficient and area-efficient switching scheme based on multi-reference for SAR ADC.
IEICE Electron. Express, 2015

Effects of coaxial through-silicon via on carrier mobility along [100] and [110] crystal directions of (100) silicon.
IEICE Electron. Express, 2015

Green phase difference coding with low switching activity for Network-on-Chip.
IEICE Electron. Express, 2015

Strategy for SAR ADC with 87.5% area saving and 99.4% switching energy reduction over conventional approach.
IEICE Electron. Express, 2015

An ultra-low-voltage self-powered energy harvesting rectifier with digital switch control.
IEICE Electron. Express, 2015

Ultra-low energy switching scheme for SAR ADC.
IEICE Electron. Express, 2015

A 0.45 V, 15.6 nW MOSFET-only sub-threshold voltage reference with no amplifiers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

A voltage doubling AC-DC converter with offset-controlled comparators for piezoelectric energy harvester.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A 19-nW 0.7-V CMOS Voltage Reference With No Amplifiers and No Clock Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A 2.1-Channel Class-D Amplifier Exploited Coupling Virtual-Audio-Image to Enhance Stereo.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A single-channel 8-bit 660 MS/s asynchronous SAR ADC with pre-settling procedure in 65 nm CMOS.
Microelectron. J., 2014

Capacitance characterization of tapered through-silicon-via considering MOS effect.
Microelectron. J., 2014

A Very Low-TC Second-Order temperature-compensated CMOS Current Reference.
J. Circuits Syst. Comput., 2014

A 2.67 fJ/c.-s. 27.8 kS/s 0.35 V 10-bit successive approximation register analogue-to-digital converter in 65 nm complementary metal oxide semiconductor.
IET Circuits Devices Syst., 2014

Temperature properties of the parasitic resistance of through-silicon vias (TSVs) in high-frequency 3-D ICs.
IEICE Electron. Express, 2014

The range alignment approach for signal acquisition system.
IEICE Electron. Express, 2014

CCS: A low-power capacitively charge-sharing transmitter for NoC links.
IEICE Electron. Express, 2014

A hybrid threshold self-compensation rectifier for RF energy harvesting.
IEICE Electron. Express, 2014

2013
A 1.33 μW 10-bit 200KS/s SAR ADC with a tri-level based capacitor switching procedure.
Microelectron. J., 2013

A Low Distortion Bootstrapped Switch for 4-Bit MDAC.
J. Circuits Syst. Comput., 2013

A 3.03 μW 10-BIT 200 KS/s SAR ADC IN 0.18 μM CMOS.
J. Circuits Syst. Comput., 2013

A Low Offset High Speed Comparator for Pipeline ADC.
J. Circuits Syst. Comput., 2013

A Low Offset Comparator for High Speed Low Power ADC.
J. Circuits Syst. Comput., 2013

A High Speed Low Power latched Comparator for SHA-Less Pipelined ADC.
J. Circuits Syst. Comput., 2013

A CMOS OTA with extremely large DC open-loop voltage gain.
IEICE Electron. Express, 2013

A highly efficient interface circuit for ultra-low-voltage energy harvesting.
IEICE Electron. Express, 2013

Thermo-mechanical performance of Cu and SiO<sub>2</sub> filled coaxial through-silicon-via (TSV).
IEICE Electron. Express, 2013

Analytical models for the thermal strain and stress induced by annular through-silicon-via (TSV).
IEICE Electron. Express, 2013

Reduction of signal reflection in high-frequency three-dimensional (3D) integration circuits.
IEICE Electron. Express, 2013

A low-jitter pulsewidth control loop with high supply noise rejection.
IEICE Electron. Express, 2013

A novel DC and PWM dual-mode dimming circuit for the WLED driver.
IEICE Electron. Express, 2013

A new stereo enhancement circuit for class-D amplifier.
IEICE Electron. Express, 2013

Erratum: The impact of trapping centers on AlGaN/GaN resonant tunneling diode [IEICE Electronics Express Vol 10 (2013) No 19 pp 20130588].
IEICE Electron. Express, 2013

The impact of trapping centers on AlGaN/GaN resonant tunneling diode.
IEICE Electron. Express, 2013

2012
Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits.
Microelectron. J., 2012

A High Precision CMOS voltage Reference without resistors.
J. Circuits Syst. Comput., 2012

A fast-locking low-jitter pulsewidth control loop for high-speed pipelined ADC.
IEICE Electron. Express, 2012

A CMOS 4.6ppm/°C curvature-compensated bandgap voltage reference.
IEICE Electron. Express, 2012

2011
Novel hybrid D/A structures for high-resolution SAR ADCs - analysis, modeling and realization.
Microelectron. J., 2011

A high-speed asynchronous array multiplier based on multi-threshold semi-static NULL convention logic pipeline.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A thermal model for the top layer of 3D integrated circuits considering through silicon vias.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

System level performance evaluation of three-dimensional integrated circuit.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A novel low THD 4-quadrant analog multiplier using feedforward compensation for PFC.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Zero-crossing distortion analysis in one cycle controlled boost PFC for Low THD.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A low-kickback preamplifier with offset cancellation for pipelined folding A/D Converter.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A 1.8V 100MS/s 10-bit pipelined folding A/D converter with 9.49 ENOB at Nyquist frequency.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
High Speed Multi-Resource Arbiter with Active Virtual Channel Allocation for Network on Chips.
J. Circuits Syst. Comput., 2010

2009
Low-power Capacitor Arrays for Charge Redistribution SAR A-D Converter in 65nm CMOS.
Proceedings of the 2009 Pacific-Asia Conference on Circuits, Communications and Systems, 2009

A Novel R-C Combination Based Pseudo-differential SAR A/D Converter in 90nm CMOS Process.
Proceedings of the 2009 Pacific-Asia Conference on Circuits, Communications and Systems, 2009

A Low Distortion CMOS Bootstrapped Switch.
Proceedings of the 2009 Pacific-Asia Conference on Circuits, Communications and Systems, 2009

A GALS Delay-insensitive Self-timed Wrapper for Network on Chips.
Proceedings of the 2009 Pacific-Asia Conference on Circuits, Communications and Systems, 2009

A Novel GALS Single-Track Protocol Asynchronous Communication Circuits.
Proceedings of the 2009 Pacific-Asia Conference on Circuits, Communications and Systems, 2009

2005
A High Accuracy Bandgap Reference with Chopped Modulator to Compensate MOSFET Mismatch.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005


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