Jiang Wu

Orcid: 0000-0002-6353-8890

According to our database1, Jiang Wu authored at least 12 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
An effective fault localization approach for Verilog based on enhanced contexts.
Frontiers Comput. Sci., October, 2024

Time-Aware Spectrum-Based Bug Localization for Hardware Design Code with Data Purification.
ACM Trans. Archit. Code Optim., September, 2024

Knowledge-Augmented Mutation-Based Bug Localization for Hardware Design Code.
ACM Trans. Archit. Code Optim., September, 2024

Strider: Signal Value Transition-Guided Defect Repair for HDL Programming Assignments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024

Simple but Powerful Beginning: Metamorphic Verification Framework for Cryptographic Hardware Design.
Proceedings of the 30th IEEE International Conference on Parallel and Distributed Systems, 2024

2023
Validating the Redundancy Assumption for HDL from Code Clone's Perspective.
Proceedings of the 2023 International Symposium on Physical Design, 2023

Mantra: Mutation Testing of Hardware Design Code Based on Real Bugs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Fault Localization for Hardware Design Code with Time-Aware Program Spectrum.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2020
Enabling Reliability-Driven Optimization Selection with Gate Graph Attention Neural Network.
Int. J. Softw. Eng. Knowl. Eng., 2020

A Highly Reliable Compilation Optimization Passes Sequence Generation Framework.
IEICE Trans. Inf. Syst., 2020

Compilation Optimization Pass Selection Using Gate Graph Attention Neural Network for Reliability Improvement.
IEEE Access, 2020

High-Reliability Compilation Optimization Sequence Generation Framework Based ANN.
Proceedings of the 20th IEEE International Conference on Software Quality, 2020


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