Jiang Wu

According to our database, Jiang Wu authored at least 16 papers between 2020 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

Debug Like a Human: Scaling LLM-based Fault Localization to Processor Design via Block-Level Instruction-Oriented Slicing.

Zizhen Liu, Xiaoguang Mao, Deheng Yang, Jiayu He, Yihao Qin, Guangda Zhang, Yan Lei, Jianjun Xu, Jiang Wu

CoRR, May, 2026

SRepair: Symbolic Regression-Based Repair for Hardware Design Code.

Zizhen Liu, Deheng Yang, Xiaoguang Mao, Jiayu He, Guangda Zhang, Yan Lei, Jiang Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2026

2025

Rtl design flaws revisited: a data-driven study of systematic bug patterns in Verilog code.

Xiankai Meng, Xiang Ji, Guangda Zhang, Jiayu He, Deheng Yang, Fangshu Chen, Jiahui Wang, Chengcheng Yu, Xinlin Zhao, Jiang Wu

J. Supercomput., September, 2025

2024

An effective fault localization approach for Verilog based on enhanced contexts.

Zhuo Zhang, Ya Li, Lei Xia, Jianxin Xue, Jiang Wu, Xiaoguang Mao

Frontiers Comput. Sci., October, 2024

Time-Aware Spectrum-Based Bug Localization for Hardware Design Code with Data Purification.

Jiang Wu, Zhuo Zhang, Deheng Yang, Jianjun Xu, Jiayu He, Xiaoguang Mao

ACM Trans. Archit. Code Optim., September, 2024

Knowledge-Augmented Mutation-Based Bug Localization for Hardware Design Code.

Jiang Wu, Zhuo Zhang, Deheng Yang, Jianjun Xu, Jiayu He, Xiaoguang Mao

ACM Trans. Archit. Code Optim., September, 2024

Strider: Signal Value Transition-Guided Defect Repair for HDL Programming Assignments.

Deheng Yang, Jiayu He, Xiaoguang Mao, Tun Li, Yan Lei, Xin Yi, Jiang Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024

Simple but Powerful Beginning: Metamorphic Verification Framework for Cryptographic Hardware Design.

Jianjun Xu, Jiang Wu, Jiayu He, Deheng Yang, Xiaoguang Mao

Proceedings of the 30th IEEE International Conference on Parallel and Distributed Systems, 2024

2023

Validating the Redundancy Assumption for HDL from Code Clone's Perspective.

Jianjun Xu, Jiayu He, Jingyan Zhang, Deheng Yang, Jiang Wu, Xiaoguang Mao

Proceedings of the 2023 International Symposium on Physical Design, 2023

Mantra: Mutation Testing of Hardware Design Code Based on Real Bugs.

Jiang Wu, Yan Lei, Zhuo Zhang, Xiankai Meng, Deheng Yang, Pan Li, Jiayu He, Xiaoguang Mao

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Fault Localization for Hardware Design Code with Time-Aware Program Spectrum.

Jiang Wu, Zhuo Zhang, Deheng Yang, Xiankai Meng, Jiayu He, Xiaoguang Mao, Yan Lei

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2020

Enabling Reliability-Driven Optimization Selection with Gate Graph Attention Neural Network.

Jiang Wu, Jianjun Xu, Xiankai Meng, Haoyu Zhang, Zhuo Zhang

Int. J. Softw. Eng. Knowl. Eng., 2020

A Highly Reliable Compilation Optimization Passes Sequence Generation Framework.

Jiang Wu, Jianjun Xu, Xiankai Meng, Yan Lei

IEICE Trans. Inf. Syst., 2020

Compilation Optimization Pass Selection Using Gate Graph Attention Neural Network for Reliability Improvement.

Jiang Wu, Jianjun Xu, Xiankai Meng, Haoyu Zhang, Zhuo Zhang, Long Li

IEEE Access, 2020

Reliable Compilation Optimization Phase-ordering Exploration with Reinforcement Learning.

Jiang Wu, Xiankai Meng, Jianjun Xu, Haoyu Zhang

Proceedings of the 2020 IEEE International Conference on Systems, Man, and Cybernetics, 2020

High-Reliability Compilation Optimization Sequence Generation Framework Based ANN.

Jiang Wu, Jianjun Xu, Xiankai Meng, Zhuo Zhang, Nan Zhang, Haoyu Zhang

Proceedings of the 20th IEEE International Conference on Software Quality, 2020