Tun Li

Proceedings of the ASSE 2021: 2nd Asia Service Sciences and Software Engineering Conference, 2021

2020

Towards functional verifying a family of systemC TLMs.

[BibT_eX]

[DOI]

Jun Ye

Qingping Tan

Frontiers Comput. Sci., 2020

Software testing without the oracle correctness assumption.

[BibT_eX]

[DOI]

Frontiers Comput. Sci., 2020

Compiling FL<sup>res</sup> on Finite Words.

[BibT_eX]

[DOI]

Wanwei Liu

Liangze Yin

Proceedings of the Dependable Software Engineering. Theories, Tools, and Applications, 2020

2015

Equivalence checking of scheduling in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2013

Bounded Model Checking of ETL Cooperating with Finite and Looping Automata Connectives.

[BibT_eX]

[DOI]

J. Appl. Math., 2013

Introduction to programming: science or art?

[BibT_eX]

[DOI]

Proceedings of the Innovation and Technology in Computer Science Education conference 2013, 2013

Efficient translation validation of high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

Translation validation of scheduling in high level synthesis.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Application specified soft error failure rate analysis using sequential equivalence checking techniques.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2011

Separation of communication and computation in SystemC/TLM modeling: A Feature-Oriented approach.

[BibT_eX]

[DOI]

Jun Ye

QingPing Tan

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

FeatureVerilog: Extending Verilog to Support Feature-Oriented Programming.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010

Feature-Oriented Refactoring Proposal for Transaction Level Models in SoCLib.

[BibT_eX]

Proceedings of the 2010 Forum on specification & Design Languages, 2010

2009

The application of Aspectual Feature Module in the development and verification of SystemC models.

[BibT_eX]

[DOI]

Jun Ye

QingPing Tan

Proceedings of the Forum on specification and Design Languages, 2009

2008

2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Explicit Model Checking Based on Integer Pointer and Fibonacci Hash.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference for Young Computer Scientists, 2008

2007

Experiences Teaching Functional Verification Techniques with Practical Designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

A Novel Collaborative Verification Environment for SoC Co-Verification.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, 2007

Coverage Driven Test Generation Framework for RTL Functional Verification.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

2006

Scheduling of Transactions Based on Extended Scheduling Timed Petri Nets for SoC System-Level Test-Case Generation.

[BibT_eX]

[DOI]

Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

2005

Applying Constraint Logic Programming to Predicate Abstraction of RTL Verilog Descriptions.

[BibT_eX]

[DOI]

Proceedings of the MICAI 2005: Advances in Artificial Intelligence, 2005

MA2TG: A Functional Test Program Generator for Microprocessor Verification.

[BibT_eX]

[DOI]

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming.

[BibT_eX]

[DOI]

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Predicate Abstraction of RTL Verilog Descriptions Using Constraint Logic Programming.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2005

Automatic functional test program generation for microprocessor verification.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Automatic Circuit Extractor for HDL Description Using Program Slicing.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2004

Design and Implementation of a Parallel Verilog Simulator: PVSim.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Assertion-based automated functional vectors generation using constraint logic programming.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

CLP Based Static Property Checking.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis: Second International Conference, 2004

Parallel verilog simulation: architecture and circuit partition.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

An Automatic Circuit Extractor for RTL Verification.

[BibT_eX]

[DOI]