Jianyu Zhong

According to our database, Jianyu Zhong authored at least 5 papers between 2015 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

A 0.19 mm² 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS.

Yan Zhu, Chi-Hang Chan, Zi-Hao Zheng, Cheng Li, Jianyu Zhong, Rui Paulo Martins

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC.

Guan-Cheng Wang, Cheng Li, Yan Zhu, Jianyu Zhong, Yan Lu, Chi-Hang Chan, Rui Paulo Martins

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017

A 12b 180MS/s 0.068mm² With Full-Calibration-Integrated Pipelined-SAR ADC.

Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016

A 12b 180MS/s 0.068mm² pipelined-SAR ADC with merged-residue DAC for noise reduction.

Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

2015

Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs.

Jianyu Zhong, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins

IEEE Trans. Circuits Syst. I Regul. Pap., 2015