Sai-Weng Sin

IEEE Trans. Circuits Syst., 2020

A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

Analysis, Design and Control of an Integrated Three-Level Buck Converter under DCM Operation.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2020

A 5 GS/s 29 mW Interleaved SAR ADC With 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications.

[BibT_eX]

[DOI]

IEEE Access, 2020

A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019

Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Design of KY Converter With Constant On-Time Control Under DCM Operation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 550- $\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

An Integrated DC-DC Converter With Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing.

[BibT_eX]

[DOI]

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

Multibit Sturdy MASH ΔΣ Modulator with Error-shaped Segmented DACs for Wideband Low-power Applications.

[BibT_eX]

[DOI]

Liang Qi

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

A 220-MHz Bondwire-Based Fully-Integrated KY Converter With Fast Transient Response Under DCM Operation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Reconfigurable and Extendable Digital Architecture for Mixed Signal Power Electronics Controller.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 10-MHz Bandwidth Two-Path Third-Order ΣΔ Modulator With Cross-Coupling Branches.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Quick and cost-efficient A/D converter static characterization using low-precision testing signal.

[BibT_eX]

[DOI]

Microelectron. J., 2018

Review and Selection Strategy for High-Accuracy Modeling of PWM Converters in DCM.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2018

A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Design and Control of An Integrated 3-Level Boost Converter under DCM Operation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Power Quality Indexes Measurement System Platform with Remote Alarm Notification.

[BibT_eX]

[DOI]

Proceedings of the IECON 2018, 2018

2017

Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

A 12b 180MS/s 0.068mm2 With Full-Calibration-Integrated Pipelined-SAR ADC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Metastablility in SAR ADCs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

A sub-1V 78-nA bandgap reference with curvature compensation.

[BibT_eX]

[DOI]

Microelectron. J., 2017

A digital PWM controlled KY step-up converter based on frequency domain ΣΔ ADC.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on Industrial Electronics, 2017

CCM operation analysis and parameters design of Negative Output Elementary Luo Converter for ripple suppression.

[BibT_eX]

[DOI]

Proceedings of the IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, Beijing, China, October 29, 2017

A 5-bit 2 GS/s binary-search ADC with charge-steering comparators.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016

Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2016

A 94-dB DR, 105-Hz bandwidth interface circuit for inertial navigation applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Integrated Circuits, 2016

A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016

An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology.

[BibT_eX]

[DOI]

Dante Gabriel Muratore

Proceedings of the ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016

A high DR multi-channel stage-shared hybrid front-end for integrated power electronics controller.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Polyphase Decomposition for Tunable Band-Pass Sigma-Delta A/D Converters.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

Split-SAR ADCs: Improved Linearity With Power and Speed Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

A background gain- calibration technique for low voltage pipelined ADCs based on nonlinear interpolation.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2012

A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2012

An ELD tracking compensation technique for active-RC CT ΣΔ modulators.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 38th European Solid-State Circuit conference, 2012

A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique.

[BibT_eX]

[DOI]

Proceedings of the 38th European Solid-State Circuit conference, 2012

A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Hybrid loopfilter sigma-delta modulator with NTF zero compensation.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2011

A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration.

[BibT_eX]

[DOI]

Proceedings of the 37th European Solid-State Circuits Conference, 2011

A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs.

[BibT_eX]

[DOI]

VLSI Design, 2010

A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 μm CMOS with minimised supply headroom.

[BibT_eX]

[DOI]

Seng-Pan U

IET Circuits Devices Syst., 2010

A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H.

[BibT_eX]

[DOI]

Proceedings of the 36th European Solid-State Circuits Conference, 2010

A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2008

Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A power-efficient capacitor structure for high-speed charge recycling SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A process- and temperature- insensitive current-controlled delay generator for sampled-data systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A pseudo-differential comparator-based pipelined ADC with common mode feedforward technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2006

A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2004

A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Quantitative noise analysis of jitter-induced nonuniformly sampled-and-held signals.

[BibT_eX]

[DOI]

Seng-Pan U