Jih-Jeen Chen

According to our database, Jih-Jeen Chen authored at least 5 papers between 1998 and 2003.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2003

Test pattern generation and clock disabling for simultaneous test time and power reduction.

Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2002

Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling.

Kuen-Jong Lee, Jih-Jeen Chen

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2000

Peak-power reduction for multiple-scan circuits during test application.

Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Broadcasting test patterns to multiple circuits.

Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998

Using a single input to support multiple scan chains.

Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998