Kuen-Jong Lee

According to our database1, Kuen-Jong Lee authored at least 117 papers between 1990 and 2021.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2017, "For contributions to low-cost testing of digital VLSI circuits".

Timeline

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Bibliography

2021
Test Chips With Scan-Based Logic Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2020
Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations.
Proceedings of the IEEE International Test Conference, 2020

Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels.
Proceedings of the IEEE International Test Conference in Asia, 2020

Efficient Prognostication of Pattern Count with Different Input Compression Ratios.
Proceedings of the IEEE European Test Symposium, 2020

2019
An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction.
IEEE Trans. Very Large Scale Integr. Syst., 2019

On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Novel Test Generation Method for Small-Delay Defects with User-Defined Fault Model.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia.
Proceedings of the IEEE International Test Conference, 2019

Time-Related Hardware Trojan Attacks on Processor Cores.
Proceedings of the IEEE International Test Conference in Asia, 2019

Deep Learning Based Test Compression Analyzer.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

Using Unstable SRAM Bits for Physical Unclonable Function Applications on Off-The-Shelf SRAM.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018
A Repair-for-Diagnosis Methodology for Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip.
IEEE Trans. Computers, 2018

Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run.
Proceedings of the IEEE International Test Conference, 2018

Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run.
Proceedings of the IEEE International Test Conference in Asia, 2018

A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Test Stimulus Compression Based on Broadcast Scan With One Single Input.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

A low power synthesis flow for multi-rate systems.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems.
Proceedings of the IEEE International Test Conference, 2017

Test generation for open and delay faults in CMOS circuits.
Proceedings of the International Test Conference in Asia, 2017

A run-pause-resume silicon debug technique for multiple clock domain systems.
Proceedings of the International Test Conference in Asia, 2017

Test Compression with Single-Input Data Spreader and Multiple Test Sessions.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
Transformation of multiple fault models to a unified model for ATPG efficiency enhancement.
Proceedings of the 2016 IEEE International Test Conference, 2016

Output bit selection methodology for test response compaction.
Proceedings of the 2016 IEEE International Test Conference, 2016

An on-chip self-test architecture with test patterns recorded in scan chains.
Proceedings of the 2016 IEEE International Test Conference, 2016

Autonomous Testing for 3D-ICs with IEEE Std. 1687.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Improve transition fault diagnosability via observation point insertion.
Proceedings of the VLSI Design, Automation and Test, 2015

A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Distinguishing dynamic bridging faults and transition delay faults.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Efficient LFSR Reseeding Based on Internal-Response Feedback.
J. Electron. Test., 2014

An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Output selection for test response compaction based on multiple counters.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

An efficient diagnosis-aware pattern generation procedure for transition faults.
Proceedings of the 2014 International Test Conference, 2014

Output-bit selection with X-avoidance using multiple counters for test-response compaction.
Proceedings of the 19th IEEE European Test Symposium, 2014

An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Counter-Based Output Selection for Test Response Compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chip.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A New LFSR Reseeding Scheme via Internal Response Feedback.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Routing-efficient implementation of an internal-response-based BIST architecture.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Accumulator-based output selection for test response compaction.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Programmable System-on-Chip for Silicon Prototyping.
IEEE Trans. Ind. Electron., 2011

Test Response Compaction via Output Bit Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

EPIDETOX: an ESL platform for integrated circuit design and tool exploration.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

A software/hardware co-debug platform for multi-core systems.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
On-Chip SOC Test Platform Design Based on IEEE 1500 Standard.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A Complete Logic BIST Technology with No Storage Requirement.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Turbo1500: Core-Based Design for Test and Diagnosis.
IEEE Des. Test Comput., 2009

A low-cost SOC debug platform based on on-chip test architectures.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Tolerance of performance degrading faults for effective yield improvement.
Proceedings of the 2009 IEEE International Test Conference, 2009

Transaction Level Modeling and Design Space Exploration for SOC Test Architectures.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Full System Simulation and Verification Framework.
Proceedings of the Fifth International Conference on Information Assurance and Security, 2009

2008
An Error Rate Based Test Methodology to Support Error-Tolerance.
IEEE Trans. Reliab., 2008

A hybrid software-based self-testing methodology for embedded processor.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard.
Proceedings of the 2008 IEEE International Test Conference, 2008

A hybrid self-testing methodology of processor cores.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A Software-Based Test Methodology for Direct-Mapped Data Cache.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
Reduction of detected acceptable faults for yield improvement via error-tolerance.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

2005
A complete memory address generator for scan based March algorithms.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

A high speed BIST architecture for DDR-SDRAM testing.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

A novel test methodology based on error-rate to support error-tolerance.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

An embedded processor based SOC test platform.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Test Power Reduction with Multiple Capture Orders.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

A Low-Cost Diagnosis Methodology for Pipelined A/D Converters.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Test pattern generation and clock disabling for simultaneous test time and power reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

A Sigma-Delta Modulation Based BIST Scheme for A/D Converters.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
An efficient BIST method for distributed small buffers.
IEEE Trans. Very Large Scale Integr. Syst., 2002

An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment.
J. Electron. Test., 2002

Guest Editorial.
J. Electron. Test., 2002

An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application.
J. Electron. Test., 2002

Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
An on-chip march pattern generator for testing embedded memory cores.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Analysis and generation of control and observation structures foranalog circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Reduction of power consumption in scan-based circuits during testapplication by an input control technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A token scan architecture for low power testing.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A Low-Power LFSR Architecture.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
An on Chip ADC Test Structure.
Proceedings of the 2000 Design, 2000

Accelerated test pattern generators for mixed-mode BIST environments.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Peak-power reduction for multiple-scan circuits during test application.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A hierarchical test control architecture for core based design.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults.
ACM Trans. Design Autom. Electr. Syst., 1999

Broadcasting test patterns to multiple circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

An Efficient BIST Method for Small Buffers.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

An Input Control Technique for Power Reduction in Scan Circuits During Test Application.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998
A graph representation for programmable logic arrays to facilitate testing and logic design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

A General Structure of Feedback Shift Registers for Built-In Self Test.
J. Inf. Sci. Eng., 1998

Concurrent Error Detection, Diagnosis, and Fault Tolerance for Switched-Capacitor Filters.
J. Inf. Sci. Eng., 1998

Using a single input to support multiple scan chains.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Built-in current sensor designs based on the bulk-driven technique.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
A practical current sensing technique for I<sub>DDQ</sub> testing.
IEEE Trans. Very Large Scale Integr. Syst., 1995

An integrated system for assigning signal flow directions to CMOS transistors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

An I<sub>DDQ</sub> Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs).
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A New Architecture for Analog Boundary Scan.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Built-in intermediate voltage testing for CMOS circuits.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
SWiTEST: a switch level test generation system for CMOS combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1992
Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

A Fast Testing Method for Sequential Circuits at the State Trasition Level.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991
Constraints for using IDDQ testing to detect CMOS bridging faults.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

1990
On the charge sharing problem in CMOS stuck-open fault testing.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

A New Method for Assigning Signal Flow Directions to MOS Transistors.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990


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