Jing-Ping Xu

According to our database, Jing-Ping Xu authored at least 14 papers between 2003 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2016

Improved interfacial quality of GaAs metal-oxide-semiconductor device with NH₃-plasma treated yittrium-oxynitride as interfacial passivation layer.

Han-Han Lu, Jing-Ping Xu, Lu Liu, Li-Sheng Wang, Pui To Lai, Wing Man Tang

Microelectron. Reliab., 2016

A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric.

Feng Ji, Jing-Ping Xu, Lu Liu, Wing Man Tang, Pui To Lai

Microelectron. Reliab., 2016

2015

A physical model on electron mobility in InGaAs nMOSFETs with stacked gate dielectric.

Y. Huang, Jing-Ping Xu, L. S. Wang, S. Y. Zhu

Microelectron. Reliab., 2015

2014

Improved performance by using TaON/SiO₂ as dual tunnel layer in Charge-Trapping nonvolatile memory.

J. X. Chen, Jing-Ping Xu, Lu Liu, X. D. Huang, Pui To Lai

Microelectron. Reliab., 2014

2010

A carrier-mobility model for high-k gate-dielectric Ge MOSFETs with metal gate electrode.

Jing-Ping Xu, X. Xiao, Pui-To Lai

Microelectron. Reliab., 2010

2009

A study on the improved programming characteristics of flash memory with Si₃N₄/SiO₂ stacked tunneling dielectric.

Lu Liu, Jing-Ping Xu, L. L. Chen, Pui To Lai

Microelectron. Reliab., 2009

2008

A 2D threshold-voltage model for small MOSFET with quantum-mechanical effects.

Jing-Ping Xu, Y. P. Li, Pui-To Lai, W. B. Chen, S. G. Xu, J. G. Guan

Microelectron. Reliab., 2008

Influence of sidewall spacer on threshold voltage of MOSFET with high-k gate dielectric.

Jing-Ping Xu, F. Ji, Pui-To Lai, J. G. Guan

Microelectron. Reliab., 2008

Effects of Ti content and wet-N₂ anneal on Ge MOS capacitors with HfTiO gate dielectric.

C. X. Li, X. Zou, Pui-To Lai, Jing-Ping Xu, C. L. Chan

Microelectron. Reliab., 2008

A fringing-capacitance model for deep-submicron MOSFET with high-k gate dielectric.

F. Ji, Jing-Ping Xu, Pui-To Lai, J. G. Guan

Microelectron. Reliab., 2008

2007

A threshold-voltage model of SiGe-channel pMOSFET without Si cap layer.

X. Zou, Jing-Ping Xu, C. X. Li, Pui-To Lai, W. B. Chen

Microelectron. Reliab., 2007

Gate leakage properties of MOS devices with tri-layer high-k gate dielectric.

W. B. Chen, Jing-Ping Xu, Pui-To Lai, Y. P. Li, S. G. Xu

Microelectron. Reliab., 2007

2004

Interfacial properties and reliability of SiO₂ grown on 6H-SiC in dry O₂ plus trichloroethylene.

Pui-To Lai, Jing-Ping Xu, H. P. Wu, C. L. Chan

Microelectron. Reliab., 2004

2003

Enhanced reliability for low-temperature gate dielectric of MOS devices by N₂O or NO plasma nitridation.

David C. T. Or, Pui-To Lai, Johnny K. O. Sin, Paul C. K. Kwok, Jing-Ping Xu

Microelectron. Reliab., 2003