Jinho Park

Affiliations:
  • Point2 Technology, Seoul, South Korea
  • TeraSquare Inc., Seoul, South Korea
  • Marvell Semiconductor, Sunnyvale, CA, USA
  • University of Washington, Department of Electrical Engineering, Seattle, WA, USA (PhD 2003)


According to our database1, Jinho Park authored at least 16 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2024
A 26-Gb/s Framed-Pulsewidth Modulation Transceiver for Extended Reach Optical Links.
IEEE J. Solid State Circuits, August, 2024

2022
A 25.78125Gbps Bi-directional Transceiver with Framed-Pulsewidth Modulation (FPWM) for Extended Reach Optical Links in 28nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2017
A 28-Gb/s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-Tracking Eye-Opening Monitor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 103.125-Gb/s Reverse Gearbox IC in 40-nm CMOS for Supporting Legacy 10- and 40-GbE Links.
IEEE J. Solid State Circuits, 2017

2016
A Power-and-Area Efficient 10 × 10 Gb/s Bootstrap Transceiver in 40 nm CMOS for Referenceless and Lane-Independent Operation.
IEEE J. Solid State Circuits, 2016

2015
An Automatic Loop Gain Control Algorithm for Bang-Bang CDRs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS.
IEEE J. Solid State Circuits, 2015

A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10- and 40-GbE standards.
Proceedings of the Symposium on VLSI Circuits, 2015

An on-chip stochastic sigma-tracking eye-opening monitor for BER-optimal adaptive equalization.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2006
A matrix amplifier in 0.18-μm SOI CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

2005
A full-range all-pass variable phase shifter for multiple antenna receivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Parasitic-aware RF circuit design and optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A 12.5 GHz RF matrix amplifier in 180nm SOI CMOS.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

RF circuit synthesis using particle swarm optimization.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Parasitic-aware design and optimization of a fully integrated CMOS wideband amplifier.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003


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