Bongjin Kim
Orcid: 0000-0001-5397-9628
According to our database1,
Bongjin Kim
authored at least 69 papers
between 2004 and 2024.
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Bibliography
2024
CTLE-Ising: A Continuous-Time Latch-Based Ising Machine Featuring One-Shot Fully Parallel Spin Updates and Equalization of Spin States.
IEEE J. Solid State Circuits, January, 2024
30.3 VIP-Sat: A Boolean Satisfiability Solver Featuring 5×12 Variable In-Memory Processing Elements with 98% Solvability for 50-Variables 218-Clauses 3-SAT Problems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
15.6 e-Chimera: A Scalable SRAM-Based Ising Macro with Enhanced-Chimera Topology for Solving Combinatorial Optimization Problems Within Memory.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
15.5 LISA: A 576×4 All-in-One Replica-Spins Continuous-Time Latch-Based Ising Computer Using Massively-Parallel Random-Number Generations and Replica Equalizations.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
A Dynamic-Precision Bit-Serial Computing Hardware Accelerator for Solving Partial Differential Equations Using Finite Difference Method.
IEEE J. Solid State Circuits, February, 2023
A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array.
IEEE J. Solid State Circuits, 2023
ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration.
IEEE J. Solid State Circuits, 2023
A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
CTLE-Ising:A 1440-Spin Continuous-Time Latch-Based isling Machine with One-Shot Fully-Parallel Spin Updates Featuring Equalization of Spin States.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A Reconfigurable lsing Machine for Boolean Satisfiability Problems Featuring Many-Body Spin Interactions.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks.
IEEE J. Solid State Circuits, 2022
A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems.
IEEE J. Solid State Circuits, 2022
CIM-Spin: A Scalable CMOS Annealing Processor With Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems.
IEEE J. Solid State Circuits, 2022
An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Guest Editorial Revolution of AI and Machine Learning With Processing-in-Memory (PIM): From Systems, Architectures, to Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications.
IEEE Open J. Circuits Syst., 2021
Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks.
IEEE J. Solid State Circuits, 2021
A 20x28 Spins Hybrid In-Memory Annealing Computer Featuring Voltage-Mode Analog Spin Operator for Solving Combinatorial Optimization Problems.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 21×21 Dynamic-Precision Bit-Serial Computing Graph Accelerator for Solving Partial Differential Equations Using Finite Difference Method.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2020
31.2 CIM-Spin: A 0.5-to-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks.
Proceedings of the International SoC Design Conference, 2020
A 65nm Logic-Compatible Embedded and Flash Memory for In-Memory Computation of Artificial Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
Mixed-Signal Circuits and Architectures for Energy-Efficient In-Memory and In-Sensor Computation of Artificial Neural Networks.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks.
Proceedings of the 2019 International SoC Design Conference, 2019
A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
2017
A 0.2-1.45-GHz Subsampling Fractional-N Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection.
IEEE J. Solid State Circuits, 2017
2016
19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit.
Proceedings of the Symposium on VLSI Circuits, 2015
Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter.
IEEE J. Solid State Circuits, 2014
True Random Number Generator circuits based on single- and multi-phase beat frequency detection.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division.
IEICE Trans. Commun., 2013
Proceedings of the 77th IEEE Vehicular Technology Conference, 2013
A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation.
IEEE J. Solid State Circuits, 2012
IEEE Commun. Lett., 2012
Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2008
A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2004
Int. J. Math. Math. Sci., 2004