Bongjin Kim

According to our database1, Bongjin Kim authored at least 37 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2020

31.2 CIM-Spin: A 0.5-to-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A 65nm Logic-Compatible Embedded and Flash Memory for In-Memory Computation of Artificial Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
Mixed-Signal Circuits and Architectures for Energy-Efficient In-Memory and In-Sensor Computation of Artificial Neural Networks.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks.
Proceedings of the 2019 International SoC Design Conference, 2019

A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A 28Gb/s transceiver with chirp-managed EDC for DML systems.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017
A 0.2-1.45-GHz Subsampling Fractional-N Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection.
IEEE J. Solid State Circuits, 2017

2016
19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Low-Complexity Tree Architecture for Finding the First Two Minima.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit.
Proceedings of the Symposium on VLSI Circuits, 2015

Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter.
IEEE J. Solid State Circuits, 2014

True Random Number Generator circuits based on single- and multi-phase beat frequency detection.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division.
IEICE Trans. Commun., 2013

Memory-Optimized Hybrid Decoding Method for Multi-Rate Turbo Codes.
Proceedings of the 77th IEEE Vehicular Technology Conference, 2013

A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation.
IEEE J. Solid State Circuits, 2012

Immediate Exchange of Extrinsic Information for High-Throughput Turbo Decoding.
IEEE Commun. Lett., 2012

Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
QC-LDPC Decoding Architecture based on Stride Scheduling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Dual-rail decoding of low-density parity-check codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2008
A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2004
Integral transforms, convolution products, and first variations.
Int. J. Math. Math. Sci., 2004


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